Package Substrate Layout for Mixed-Voltage Wiring Reliability
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Solution Overview
Problem
In semiconductor packages with mixed operating voltages, the potential difference between wirings can lead to increased electric field migration, reducing reliability, and spacing these wirings apart to avoid defects results in increased substrate size, contradicting the trend of downsizing semiconductor devices.
Innovation Solution
A package substrate design where wiring layers with the same operating voltage overlap in a plan view, while those with different voltages are spaced apart by predetermined distances, using a multilayer structure with alternating wiring and insulating layers, and vias to maintain reliability without increasing substrate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring layers with different operating voltages are spaced apart by predetermined distances to reduce electric field migration, then reliability is improved, but substrate size increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple wiring layers in the build-up structure. Wiring layers with different operating voltages are arranged in different vertical levels (e.g., first wiring layer at first potential, second wiring layer at second potential), allowing electrical isolation through the insulating layer between layers. This three-dimensional arrangement reduces the need for large horizontal spacing while maintaining reliability.
Solution Approach 2:
The patent combines multiple functions into the build-up layer structure: the insulating layer serves both as electrical isolation between wiring layers with different potentials and as a structural bonding layer. The build-up layer integrates wiring layers, insulating layers, and via holes into a unified multilayer configuration that achieves both electrical separation and mechanical integrity without requiring additional spacing.
2Reliability
If wiring layers with different operating voltages are spaced apart horizontally, then electric field migration is reduced, but the substrate area increases
Solution Approach 1:
The patent transitions from two-dimensional horizontal spacing to three-dimensional vertical stacking. Wiring layers are arranged at different vertical levels within the build-up structure, with insulating layers separating them. This allows electrical isolation without requiring large horizontal distances, thereby reducing substrate area while maintaining resistance to electric field migration.
Solution Approach 2:
The patent implements a nested multilayer structure where wiring layers are embedded within the build-up layer at different vertical levels. Each wiring layer is nested within its own insulating layer environment, and multiple wiring layers are nested within the same substrate volume. This nested arrangement achieves electrical isolation through vertical layering rather than horizontal separation, reducing overall substrate area.
Data Source
AI summary
A package substrate on which a semiconductor chip in which circuit elements having different operating voltages exist in a mixed manner is mounted on a front surface side thereof, and in which electrical paths extending from the front surface side to a back surface side are formed for each of the operating voltages. IN the package substrate, the wiring layers having the different operating voltages are arranged so as to be spaced apart by predetermined distances in accordance with the operating voltages, and the wiring layers having the same operating voltage are arranged so as to overlap with each other in a plan view at least in the build-up layer.