Semiconductor Package Terminal Plating for Solder Crack Resistance
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Solution Overview
Problem
Solderability issues in semiconductor package assemblies, particularly in Quad Flat Pack No-lead (QFN) and flat lead products, lead to solder cracks during thermal cycling tests due to copper oxidation and uneven stress distributions, resulting in limited solder fillet formation and increased crack occurrences.
Innovation Solution
A method involving a lead frame with exposed terminals plated with the same metal material, such as copper, and optionally subjected to surface roughening and additional tin plating, to enhance solder fillet formation and reliability, thereby reducing stress concentrations and crack occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tin plating technique is applied after sawing process to prevent copper oxidation, then solderability is improved, but manufacturing complexity increases and additional process steps are required
Solution Approach 1:
The patent applies plating with the same metal material (copper) on the terminals before encapsulation, preventing copper oxidation in advance. This preliminary plating action eliminates the need for subsequent tin plating after sawing, reducing manufacturing complexity while maintaining solderability.
Solution Approach 2:
The patent uses the same metal material (copper) for both the lead frame terminals and the plating layer, creating a homogeneous structure. This eliminates material interfaces and simplifies the manufacturing process by removing the need for multi-material plating sequences.
2Reliability
If wettable flank features by step cut or dimple are adopted at terminals side wall, then solder fillet joint is formed at exterior locations, but solder fillets are not formed at interior locations where stress concentrations occur
Solution Approach 1:
The patent applies a uniform copper plating layer across all terminal surfaces (both exterior and interior side walls), ensuring consistent solderability and fillet formation at all locations. This local quality enhancement through plating addresses the specific problem of interior location soldering without requiring complex geometric modifications.
Solution Approach 2:
The patent changes the surface properties of the terminals by applying a copper plating layer, which modifies the wettablity parameter of the terminal surfaces. This parameter change enables consistent solder fillet formation at both exterior and interior locations without requiring geometric modifications like step cuts or dimples.
3Ease of manufacture
If copper terminals are left unplated to maintain manufacturing simplicity, then manufacturing process is simplified, but copper oxidation occurs leading to solder cracks during thermal cycling
Solution Approach 1:
The patent maintains manufacturing simplicity by using the same copper material for both the terminal base and the plating layer, creating a homogeneous single-material structure. This eliminates the complexity of multi-material plating while preventing copper oxidation and ensuring solder joint reliability.
Solution Approach 2:
The patent uses a thin copper plating layer that serves as a protective barrier against oxidation. This thin layer is cost-effective and simple to apply, providing long-term protection against oxidation without requiring complex manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in more even stress distribution, reduced solder crack occurrences, and improved solder joint reliability in semiconductor package assemblies, as demonstrated by reduced solder strain during thermal cycling tests.
Implementation Method 1
plating the exposed portion of the at least two terminals with a metal plating material, with the metal plating material being the same as the metal material of the lead frame
Implementation Method 2
solder fillet formation is purposely promoted to enhance the solder joint reliability
Implementation Method 3
a good solder fillet joint to be created at those locations
Implementation Method 4
encapsulating the at least one silicon die structure and the at least two terminals with a molding resin leaving at least a portion of the at least two terminals exposed
Implementation Method 5
thermal expansion mismatch between the solder material, the lead frame material and the PCB
Data Source
Figure 1A~1C
Figure 2A~2D
Figure 3A~3C
AI summary
According to a first example of the disclosure, a method for manufacturing a semiconductor package assembly is proposed, which results in a semiconductor package assembly with a more even distributed stress concentrations, reduced solder crack occurrences and limited solder filler joint connections. The method comprises the steps of forming at least one semiconductor package by means of the sub-steps: providing a lead frame made from a metal material having a first frame side and a second frame side opposite to the first frame side as well as having at least two terminals; providing at least one silicon die structure having a first die side and a second die side opposite to the first side with its second die side on the first frame side of the lead frame; electrically and mechanically attaching the at least one silicon die structure to the terminals of the lead frame; and encapsulating the at least one silicon die structure and the plurality of terminals with a molding resin leaving at least a portion of at least two terminals exposed, thereby forming at least one encapsulated semiconductor package assembly; wherein the method further comprises the step of plating the exposed portions of the at least two terminals with a metal plating material, with the metal plating material being the same as the metal material of the lead frame.