Semiconductor Package Test Pad for Pre-Stack Defect Inspection
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Solution Overview
Problem
In semiconductor packages, the presence of defective chips can lead to malfunctioning of both defective and normal chips, as they are often stacked together, resulting in inefficient performance and reduced reliability.
Innovation Solution
A semiconductor package design incorporating a test pad structure that allows for the inspection of defects in chips before final assembly, utilizing a base with bonding structures and insulating layers to ensure proper electrical connections and heat dissipation, while enabling the identification of defective chips to prevent malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are stacked together to reduce package thickness, then miniaturization is achieved, but the risk of defective chips causing malfunction increases
Solution Approach 1:
The patent implements a test pad structure that enables defect inspection of semiconductor chips before they are finally stacked and assembled into the package. This preliminary testing action allows defective chips to be identified and removed prior to final assembly, preventing them from causing malfunction in the stacked configuration. The test pad includes a test electrode that contacts the chip surface through the bonding structure, enabling electrical testing without requiring complete package assembly.
2Productivity
If chips are stacked sequentially to achieve miniaturization, then productivity is improved, but defect detection capability deteriorates
Solution Approach 1:
The bonding structure is designed to expose a test pad surface that allows electrical contact with the semiconductor chip during or after the bonding process but before final package completion. This enables defect detection to be performed as a preliminary action in the manufacturing sequence, maintaining high productivity by integrating testing into the assembly flow rather than requiring separate inspection steps after complete assembly.
Solution Approach 2:
The test pad structure acts as an intermediary element between the bonding structure and the chip being tested. It provides a dedicated test electrode that can contact the chip surface through the bonding interface, enabling defect detection without interfering with the normal bonding and stacking process. This intermediary structure facilitates easy electrical access for testing while maintaining the miniaturized stacked configuration.
Data Source
AI summary
A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.