Semiconductor Package Test Paths for Redistribution Layer Reliability

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving high electrical reliability and efficient testing of redistribution layers and conductive vias, particularly in package-on-package configurations, where multifunctionality and integration are critical but not adequately addressed.

Innovation Solution

The semiconductor package design includes a redistribution layer with conductive lines, vias, and pads connected to external terminals, allowing for electrical paths that can be tested using multiple external connection terminals, ensuring high reliability and efficient testing across layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor packages are used, then manufacturing is simpler, but electrical reliability and testing capability are insufficient

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The package structure is divided into distinct functional layers: lower redistribution layer with test terminals, semiconductor chip, upper redistribution layer with test terminals, and substrate. This segmentation allows independent optimization of each layer for reliability while maintaining overall manageability through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Test terminals are incorporated into the redistribution layers during manufacturing, enabling electrical testing of the package structure before final assembly and deployment. This preliminary testing capability ensures reliability is verified early in the process.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If conventional testing methods are used, then testing process is simpler, but testing sensitivity and coverage are insufficient

Engineering Contradiction:
Improvetesting sensitivityVSAvoidtesting structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The external connection terminals serve dual functions: they provide electrical connection for normal package operation and simultaneously serve as test terminals for electrical testing of the redistribution layers and conductive vias. This multi-functionality enables comprehensive testing without adding separate dedicated test structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The electrical test paths are configured to provide feedback on the electrical integrity of conductive lines and vias by measuring electrical characteristics through the external connection terminals. This feedback mechanism enables detection and characterization of electrical defects.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If package-on-package configuration is implemented, then multifunctionality is improved, but electrical reliability and testing capability become more challenging

Engineering Contradiction:
ImprovemultifunctionalityVSAvoidelectrical reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The package-on-package structure is segmented into distinct upper and lower packages, each with their own redistribution layers and test terminals. This segmentation allows independent testing and reliability verification of each package while maintaining their integrated multifunctional operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each package in the package-on-package configuration incorporates test terminals and electrical test paths during manufacturing, enabling preliminary electrical testing of inter-package connections and individual package integrity before final system assembly and deployment.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240071845A1Semiconductor package and package-on-package having the same
Publication Date: 2024.02.29 SAMSUNG ELECTRONICS CO LTD
  • US20240071845A1 patent drawing
  • US20240071845A1 patent drawing
  • US20240071845A1 patent drawing

AI summary

A semiconductor package includes: a redistribution layer including a plurality of conductive lines; a plurality of conductive vias each connected to at least one of the plurality of conductive lines; and a plurality of lower pads each connected to one of the plurality of conductive vias; a semiconductor chip on the redistribution layer; and a plurality of external connection terminals attached to the plurality of lower pads; and a plurality of electrical paths, wherein each of the plurality of electrical paths includes at least one of the plurality of conductive lines and at least one of the plurality of conductive vias. The plurality of electrical paths is configured for testing the plurality of conductive lines and the plurality of conductive vias and is connected to at least four of the external connection test terminals.