Semiconductor Package Trench Capacitors for Power Noise Control
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Solution Overview
Problem
Current semiconductor packages face challenges in enhancing reliability and integration while effectively managing power signal noise, with existing solutions often requiring complex processes and increased manufacturing costs.
Innovation Solution
A semiconductor package design featuring a redistribution substrate with trenches, a semiconductor chip, capacitor chips, and an under-fill layer, where the capacitor chips are integrated within the trenches of the redistribution substrate, enhancing noise removal and integration efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor chips are integrated within trenches of the redistribution substrate, then integration density and noise management are improved, but manufacturing complexity increases
Solution Approach 1:
The capacitor chips are nested within the trenches of the redistribution substrate, with the under-fill material filling the remaining space. This nesting approach allows the capacitor chips to be integrated within the substrate structure, improving noise management while utilizing the three-dimensional space efficiently.
Solution Approach 2:
The design transitions from a two-dimensional surface mounting approach to a three-dimensional integration by placing capacitor chips within vertical trenches. This dimensional change allows better noise management through closer proximity to the power signals while maintaining compact integration.
2Quantity of substance
If capacitor chips are integrated within trenches of the redistribution substrate, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The redistribution substrate is segmented into multiple trenches that can accommodate capacitor chips at different locations. This segmentation allows for modular integration, where capacitor chips are placed in specific trenches based on noise management requirements, thereby increasing integration density in a systematic manner.
Solution Approach 2:
Capacitor chips are nested within the trenches, utilizing the vertical space within the substrate. This nesting approach increases the quantity of capacitor chips that can be integrated per unit area of the substrate, thereby improving integration density without significantly expanding the overall package footprint.
3Object-affected harmful factors
If capacitor chips are mounted on the bottom surface of the semiconductor chip, then noise management is improved, but device complexity increases
Solution Approach 1:
The capacitor chips are extracted from the traditional placement on the bottom surface of the semiconductor chip and repositioned within the trenches of the redistribution substrate. This extraction allows the capacitors to be closer to the power signal sources while simplifying the overall device structure by integrating them into the substrate rather than requiring separate mounting steps.
Solution Approach 2:
The under-fill material acts as an intermediary between the capacitor chips and the surrounding structures. It provides mechanical support and electrical isolation, enabling the capacitor chips to be effectively integrated within the trenches while managing their interaction with adjacent components and reducing noise coupling.
Data Source
AI summary
Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.