Semiconductor Package Via Patterning for Fine Redistribution Wiring
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Solution Overview
Problem
The existing methods for manufacturing semiconductor packages face challenges in forming fine via holes in insulating layers with photosensitive insulating materials, as the resolution of these materials is lower than that of conventional photoresist patterns, making it difficult to achieve the required fine line widths and pitches for redistribution wirings.
Innovation Solution
A method involving a double patterning process using two separate etching processes to form first and second via holes in the insulating layers, allowing for the creation of finer diameters and pitches, thereby overcoming the resolution limitations of the photosensitive insulating materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photosensitive insulating layer (PID) is used in the redistribution wiring layer, then the insulating layer can be formed, but the resolution of the insulating layer is lower than that of existing photoresist patterns, making it difficult to form fine via holes
Solution Approach 1:
The patent divides the via hole formation process into two separate photo etching processes: a first photo etching process to form initial via holes, and a second photo etching process to form additional via holes. This segmentation allows each process to target specific via hole locations independently, overcoming the resolution limitations of the PID material by using high-resolution photoresist patterns for each step.
Solution Approach 2:
The first photo etching process is performed as a preliminary action to form initial via holes before the second photo etching process. This preliminary formation of via holes allows subsequent redistribution wirings to be accurately positioned and connected to the appropriate via holes, achieving fine line widths and pitches that would be difficult to achieve in a single step.
2Manufacturing precision
If the diameter and pitch of via holes are reduced to match fine redistribution wirings, then electrical connectivity can be improved, but the lower resolution of the photosensitive insulating layer makes it difficult to achieve the required fineness
Solution Approach 1:
The via hole formation is segmented into two distinct photo etching processes, each with its own photoresist layer and etching conditions. This allows the manufacturing process to achieve fine via hole dimensions by dividing the complex task into two manageable steps, each optimized for specific via hole locations and dimensions.
Solution Approach 2:
The patent changes the parameters of the photo etching process by performing two separate processes with different photoresist patterns. Each process uses appropriately sized opening patterns that, when combined, produce the final fine via hole structure. This parameter change from a single high-density pattern to two separate patterns makes the manufacturing process more feasible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor packages with finer redistribution wirings, improving the electrical connectivity and reducing the limitations imposed by the lower resolution of the insulating materials, leading to more efficient semiconductor package manufacturing.
Implementation Method 1
coating a photosensitive insulating material layer of the first insulating layer; and performing a curing process on the photosensitive insulating material layer
Implementation Method 2
performing an exposure process on the first photoresist layer using a first exposure mask; performing a development process to form a first photoresist pattern
Data Source
AI summary
A method includes: forming a first photoresist layer on a first insulating layer; forming a first photoresist pattern having first opening patterns using a first exposure mask; etching the first insulating layer using the first photoresist pattern to form first via holes; removing the first photoresist pattern; forming a second photoresist layer on the first insulating layer; forming a second photoresist pattern having second opening patterns using a second exposure mask; etching the first insulating layer using the second photoresist pattern to form second via holes; removing the first photoresist pattern; forming a redistribution wiring layer on the first insulating layer, the redistribution wiring layer having first redistribution wirings connected to first bonding pads under the first insulating layer through the via holes; and mounting a semiconductor chip on the redistribution wiring layer, the semiconductor chip comprising chip pads connected to the first redistribution wirings.