Semiconductor Package Via Layout for Wider Redistribution Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of electronic components and packaging to achieve higher integration density, requiring innovative methods for forming package structures that allow for smaller, more efficient integration of integrated circuit dies and improved routing capabilities.
Innovation Solution
The process involves using a carrier substrate with a release layer, adhering integrated circuit dies, forming encapsulants, seed layers, and conductive features, and creating front side redistribution structures with dielectric layers and metallization patterns to increase spacing between through vias and metallization patterns, enabling wider routing lines and more efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated circuit dies are packaged in smaller packages to achieve higher integration density, then the area occupied by each package is reduced, but the routing capabilities and spacing between conductive elements are compromised
Solution Approach 1:
The patent introduces a via structure that extends vertically through the package, utilizing the third dimension (depth) to create additional routing paths. This allows electrical connections to be made in the vertical direction rather than only in the planar direction, effectively adding a dimensional aspect to the routing capability and resolving the contradiction between reduced package area and maintained routing functionality.
Solution Approach 2:
The via structure is nested within the package body, with the via extending from the first major surface through the package to the second major surface. This nested configuration allows the routing element to be contained within the compact package volume, achieving both small package area and adequate routing capability by utilizing the internal three-dimensional space efficiently.
2Ease of operation
If the spacing between through vias and metallization patterns is increased to enable wider routing lines, then the routing capability is improved, but the area occupied by the package increases
Solution Approach 1:
The via structure utilizes the vertical dimension to create routing paths, allowing wider effective routing capability without increasing the planar footprint. By routing through the depth of the package rather than only across the surface, the design achieves improved routing capability while maintaining compact package dimensions.
Solution Approach 2:
The package structure employs thin dielectric layers and flexible metallization patterns that can be configured to accommodate the via structure. These thin film structures allow for adequate spacing between conductive elements to enable wider routing lines while minimizing the overall package area through efficient use of the three-dimensional space.
Data Source
AI summary
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.