Electronic Package Via Structure for Wiring Complexity
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Solution Overview
Problem
Conventional package structures face challenges in high-frequency, high-speed operations due to increased complexity and cost as the number of integrated functional chips grows, particularly in maintaining suitable line width/line spacing specifications and yield during the wiring process for multi-chip integration.
Innovation Solution
The introduction of an electronic package structure where a first electronic component, with a smaller vertically projected area, electrically bridges multiple second electronic components via a circuit layer, reducing the complexity of the wiring process and allowing for larger line width/line spacing specifications while minimizing the number of circuit layers, thus improving yield and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of functional chips integrated is increased, then the functionality and performance of the electronic package is improved, but the pitch between contacts becomes smaller and the wiring process becomes more challenging, resulting in higher manufacturing cost
Solution Approach 1:
The patent introduces a via structure that penetrates through the encapsulant layer to establish vertical electrical connections between functional chips. This three-dimensional wiring approach replaces traditional planar wiring, allowing signals to pass through the encapsulant rather than requiring complex surface routing, thereby simplifying the wiring process for multi-chip integration
Solution Approach 2:
The via structure acts as an intermediary element that bridges the electrical connection between functional chips mounted on opposite sides of the encapsulant. This mediator enables direct vertical connectivity through the encapsulant layer, eliminating the need for complex lateral wiring paths and reducing manufacturing complexity
2Manufacturing precision
If the line width/line spacing specifications are made larger, then the wiring process becomes easier and yield improves, but the pitch between contacts cannot be reduced sufficiently for high-density integration
Solution Approach 1:
The via structure enables vertical signal transmission through the encapsulant, transitioning from two-dimensional surface wiring to three-dimensional space utilization. This allows larger line width/spacing specifications to be maintained on the chip surfaces while achieving high-density integration through vertical connectivity, thereby improving yield without compromising contact pitch reduction
3Adaptability or versatility
If the number of circuit layers is increased to accommodate more functional chips, then the connectivity is improved, but the manufacturing cost increases and yield decreases
Solution Approach 1:
The via structure provides a vertical connection path through the encapsulant, enabling electrical connectivity between functional chips without requiring additional lateral circuit layers. This vertical interconnection approach maintains connectivity while reducing the number of circuit layers needed, thereby improving manufacturing yield and reducing costs
Data Source
AI summary
An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.