Semiconductor Package Voltage Calibration to Eliminate IR Drop
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Solution Overview
Problem
Existing power management units in semiconductor devices face limitations in flexibility and accuracy during output voltage calibration due to varying calibration patterns and interference from printed circuit boards, relays, and sockets, leading to inaccurate results.
Innovation Solution
A voltage calibration circuit comprising a voltage monitor, calibration, and storage circuit that calculates a voltage-code graph and adjusts output levels based on target codes, enabling flexible and efficient calibration within the semiconductor package without specific patterns, and mitigating IR drop effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage calibration is performed using external devices (PCB, relays, sockets), then calibration can be conducted, but IR drop occurs resulting in inaccurate calibration
Solution Approach 1:
The patent extracts the voltage calibration function from external devices (PCB, relays, sockets) and implements it directly within the semiconductor package. The calibration circuit is integrated into the package substrate, eliminating the need for external calibration paths that cause IR drop. This allows voltage calibration to be performed using only the semiconductor package itself, removing the harmful IR drop effect caused by external connection paths.
2Adaptability or versatility
If different power management units use different calibration patterns, then each unit can be calibrated, but flexibility and efficiency are limited
Solution Approach 1:
The patent implements a universal calibration circuit that can calibrate multiple types of power management units (DC-DC converters, LDOs, voltage regulators) using a single integrated calibration path. The calibration circuit includes a voltage monitor and adjustable elements that can work with different PMU types without requiring different external patterns. This multi-functional calibration system improves flexibility while reducing the complexity of managing multiple calibration patterns.
Solution Approach 2:
The calibration circuit is designed to perform self-calibration within the semiconductor package without requiring external calibration devices or complex external patterns. The voltage monitor circuit automatically measures output voltages and the calibration elements adjust accordingly, enabling the system to calibrate itself using only internal resources. This self-service capability greatly improves calibration flexibility and efficiency.
3Ease of manufacture
If pin headers are not connected to the package, then package design is simplified, but voltage screening can only be performed during circuit probing stage
Solution Approach 1:
The patent implements preliminary voltage calibration action by integrating the calibration circuit directly into the semiconductor package during manufacturing. The calibration can be performed during the circuit probing stage or function test stage without requiring separate external calibration steps. By having the calibration capability built-in from the start, the system eliminates the need for pin headers while maintaining the ability to perform voltage screening and calibration efficiently during the manufacturing process.
Data Source
AI summary
A voltage calibration circuit arranged in a chip and comprising a voltage monitor circuit, a calibration circuit and a storage circuit is provided. The voltage monitor circuit is coupled to at least one power management unit of the chip and configured to: calculate a voltage-code graph based on a received reference voltage and a received divided voltage; and output at least one output code based on the voltage-code graph and at least one output voltage received from the power management unit(s). The calibration circuit is coupled to the voltage monitor circuit and the power management unit(s), and configured to receive the output code(s) and adjust an output level of the power management unit(s) based on the output code(s) and a target code. The storage circuit is coupled to the calibration circuit, and configured to store the voltage-code graph and the output level of the power management unit(s).