Semiconductor Package Voltage Regulator With External TDV Power Routing
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Solution Overview
Problem
The formation of power through silicon vias (TSV) in semiconductor packages increases area occupation and cost, and there is a need to reduce these factors while improving the form factor and electrical connectivity between top and bottom dies.
Innovation Solution
Implementing through dielectric vias (TDVs) outside the semiconductor die that houses the CPU/GPU, coupled with an integrated voltage regulator (IVR) to provide regulated power to other semiconductor dies, reducing processing steps and cost while enhancing the form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power through silicon vias (TSV) is implemented in semiconductor packages, then electrical connectivity between top and bottom dies is achieved, but area occupation and manufacturing cost increase
Solution Approach 1:
The patent extracts the power delivery function from the silicon die interior by implementing through dielectric vias (TDVs) in the package substrate rather than using through silicon vias (TSVs) within the dies. This separates the power delivery infrastructure from the active die area, reducing the area occupation on the semiconductor dies while maintaining electrical connectivity between top and bottom dies through the package substrate.
2Reliability
If power through silicon vias (TSV) is implemented in semiconductor packages, then electrical connectivity between top and bottom dies is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the power delivery function from the silicon die interior by implementing through dielectric vias (TDVs) in the package substrate rather than using through silicon vias (TSVs) within the dies. This separation reduces manufacturing complexity and cost by avoiding the expensive TSV formation processes on the dies themselves, while still achieving the required electrical connectivity through the package substrate.
Solution Approach 2:
The patent introduces the package substrate as an intermediary structure that carries the power delivery function. Instead of directly connecting top and bottom dies through expensive TSVs in the silicon, the TDVs in the package substrate serve as an intermediate power delivery path, reducing the manufacturing burden on the dies themselves while maintaining the electrical connectivity function.
3Ease of manufacture
If through dielectric vias (TDVs) are implemented outside the semiconductor die, then processing steps and cost are reduced, but area occupation in the package increases
Solution Approach 1:
The patent moves the power delivery infrastructure from the vertical dimension (through-silicon vias penetrating the die thickness) to the horizontal dimension (through dielectric vias in the package substrate). This dimensional shift relocates the area occupation from the precious die area to the package substrate area, simplifying die processing while distributing the area requirement across the larger package footprint.
Data Source
AI summary
A semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. The through via is disposed outside of and adjacent to the second semiconductor die. The through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.