Semiconductor Package Waveguide Alignment for Low-Loss Photonics

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving cost-effective and bandwidth-scalable photonics semiconductor packages with relaxed accuracy requirements for optical fiber assembly, particularly in integrating complex photonic components with high alignment precision and reduced optical loss.

Innovation Solution

A semiconductor package manufacturing method involving a redistribution structure, a supporting layer, and a transition waveguide structure, where the supporting layer is formed over the redistribution structure with connectors, and the semiconductor device is bonded to these connectors, with the transition waveguide optically coupled to the device waveguide, allowing for improved alignment accuracy and reduced optical loss through the use of a broadened alignment width and refractive index design for total internal reflection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional semiconductor packaging methods are used, then manufacturing simplicity is maintained, but alignment accuracy and optical transmission efficiency deteriorate

Engineering Contradiction:
Improvealignment accuracyVSAvoidpackage structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the packaging structure into distinct functional layers: supporting layer, redistribution layer, and encapsulant layer. Each layer performs specific functions (mechanical support, electrical redistribution, and optical protection respectively), enabling precise alignment through structured segmentation while maintaining manufacturing feasibility through modular assembly processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical stacking dimension to achieve horizontal alignment precision. By positioning connectors and waveguides in different vertical planes (supporting layer at bottom, redistribution layer in middle, encapsulant on top), the design achieves three-dimensional spatial optimization that improves two-dimensional alignment accuracy while managing complexity through vertical separation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If high alignment precision is achieved through complex structures, then optical loss is reduced, but manufacturing cost increases

Engineering Contradiction:
Improveoptical lossVSAvoidmanufacturing cost
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent implements preliminary alignment features during the manufacturing process, such as pre-positioned connectors and pre-formed waveguide structures. The supporting layer is prepared with embedded alignment markers and connector positions before final assembly, enabling automated pick-and-place operations to achieve high precision alignment without requiring complex post-assembly adjustment mechanisms, thereby reducing both optical loss and manufacturing cost.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The redistribution layer acts as an intermediary between the supporting layer and the optical components. It provides a transition zone that facilitates precise electrical and optical coupling while maintaining mechanical stability. This intermediary layer enables standardized connection interfaces that reduce alignment complexity and manufacturing cost while minimizing optical loss through optimized signal transmission paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If bandwidth scalability is enhanced through advanced packaging, then transmission capacity increases, but manufacturing complexity increases

Engineering Contradiction:
Improvebandwidth scalabilityVSAvoidpackaging process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the supporting layer and redistribution layer with universal, multi-functional characteristics. The supporting layer provides mechanical support, electrical grounding, and thermal management functions simultaneously. The redistribution layer handles both electrical signal routing and optical alignment reference functions. This multi-functionality enables bandwidth scalability through standardized interfaces that can accommodate different data rates without requiring fundamentally different packaging approaches, thereby enhancing productivity while controlling complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables cost-competitive photonics semiconductor packages with enhanced bandwidth scalability and relaxed accuracy requirements, improving alignment accuracy and reducing optical loss during assembly, thus facilitating more efficient optical signal transmission.

Implementation Method 1

refractive index design for total internal reflection

Methodology Applied
Scientific EffectTotal internal reflection: Total Internal Reflection

Data Source

PatentUS12176282B2Manufacturing method of semiconductor package
Publication Date: 2024.12.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12176282B2 patent drawing
  • US12176282B2 patent drawing
  • US12176282B2 patent drawing

AI summary

A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.