Package on Wide I/O Silicon Using Bumpless Build-Up Layer
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Solution Overview
Problem
Current three-dimensional packaging technologies face challenges in reducing power consumption, minimizing package form factor, and enhancing interconnect speed, particularly due to the limitations of solder connections and thermal expansion mismatches in die-to-substrate coefficients, which affect I/O and power delivery performance.
Innovation Solution
The implementation of bumpless build-up layer (BBUL) technology, which eliminates solder ball interconnections and uses direct physical contact between dies and substrates, along with through-silicon vias and build-up layers of conductive material separated by dielectric material, to facilitate efficient connectivity and reduce stress on low-k interlayer dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder ball interconnections are used for die-to-die stacking, then electrical connectivity between dies is achieved, but stress on low-k interlayer dielectric materials increases and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the solder ball interconnection layer from the traditional flip-chip packaging architecture. By removing the solder balls and replacing them with direct die-to-substrate bonding, the source of thermal expansion stress is eliminated, thereby reducing stress on the low-k interlayer dielectric materials while maintaining electrical connectivity through alternative bonding methods
Solution Approach 2:
The patent introduces an intermediary bonding layer or eutectic bonding interface between the die and substrate that serves as a stress-compliant interface. This intermediary layer accommodates thermal expansion mismatches between different materials, reducing the transmission of stress to the sensitive low-k interlayer dielectric materials while maintaining reliable electrical connectivity
2Reliability
If solder connections are used in die-to-substrate stacking, then I/O performance is achieved, but package form factor increases and power delivery performance deteriorates
Solution Approach 1:
The patent removes the solder ball interconnection layer and associated underfill materials from the packaging architecture, directly reducing the vertical height and lateral footprint of the package. This extraction of unnecessary intermediate layers enables a more compact package form factor while maintaining I/O performance through direct bonding interfaces
Solution Approach 2:
The patent transitions from a traditional flip-chip architecture with significant vertical separation (multiple layers including solder balls and underfill) to a more integrated stacked architecture where dies are directly bonded with minimal intermediate layers. This dimensional consolidation reduces the overall package height and allows for more efficient space utilization
3Reliability
If solder ball interconnections are used, then electrical connectivity is established, but thermal management performance deteriorates
Solution Approach 1:
The patent extracts the solder ball interconnection layer that acts as a thermal barrier, replacing it with direct die-to-substrate bonding that provides superior thermal pathways. This removal of thermally resistive intermediate layers enables more efficient heat dissipation from the active die regions to the substrate heat sink
Solution Approach 2:
The patent employs composite bonding structures that combine materials with superior thermal conductivity at the die-substrate interface. By using eutectic bonding layers or other thermally conductive bonding materials instead of traditional solder balls, the interface thermal resistance is reduced, enabling more effective thermal management while maintaining electrical connectivity
Data Source
AI summary
An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points.