Packaged Chip Signal Transmission via Substrate Capacitors

The patent extracts the bonding function from traditional wire bonds and integrates it directly into the package substrate through conductive vias and trace patterns. The bond pads on the chip are directly bonded to contact pads on the package substrate, eliminating the need for separate wire bond interconnects. This extraction of the bonding function from wires to substrate resolves the contradiction by providing lower inductance paths while maintaining manufacturing simplicity through standard substrate fabrication processes.

The patent merges multiple functions into the package substrate: the substrate serves as both the mechanical support structure and the electrical interconnect medium. Conductive traces and vias are integrated directly into the substrate layers, combining the functions of structural support, signal transmission, and impedance control in a single component. This merging eliminates the need for separate wire bonds while maintaining package simplicity.

The patent transitions from two-dimensional wire bond interconnects to three-dimensional substrate-integrated conductors. Conductive vias extend vertically through multiple substrate layers, providing additional dimensional space for current flow. This vertical dimensionality allows for effective impedance control and reduced inductance without increasing the horizontal package footprint, as the enhanced conductor cross-section is achieved through vertical stacking rather than lateral expansion.

The patent employs composite substrate structures with multiple conductive layers separated by dielectric materials. The package substrate comprises conductive traces in one layer, vias connecting to contact pads in another layer, and additional ground or power planes in subsequent layers. This composite construction provides enhanced effective cross-sectional area for current flow and improved impedance control while maintaining compact package dimensions through efficient vertical stacking.

The patent extracts the interconnect function from external wire bonds and integrates it directly into the package substrate through short conductive vias and trace patterns. The signal path is established through the substrate itself rather than through long external wires, dramatically reducing the effective interconnect length. This extraction enables high-frequency signal transmission while maintaining flexible package and chip layout options.

The package substrate acts as an intermediary medium that provides direct electrical connection between chip bond pads and package terminals. Instead of using long wire bonds as intermediaries, the substrate's integrated conductive paths serve as the intermediate connection medium, providing shorter, lower-inductance signal paths while enabling flexible mechanical and electrical design.

The patent applies local quality enhancements at critical signal transition points within the package substrate. Contact pads, via structures, and trace geometries are specifically designed with controlled dimensions, materials, and configurations to match impedance at boundaries between different media (chip substrate interface, via transitions, trace connections). This localized impedance control prevents reflections at critical interfaces without requiring complex overall package restructuring.

The patent employs parameter optimization of conductive trace and via dimensions, materials, and geometries to control impedance characteristics. By adjusting parameters such as trace width, via diameter, dielectric thickness, and conductor material properties, the package substrate achieves impedance matching across frequency ranges. These parameter changes enable reduced signal reflections and improved high-frequency performance while maintaining standard substrate fabrication processes.