Packaged Chip Test Structure Using Retained Top Metal Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional methods for testing electrical performance of packaged chips result in poor short-circuiting effects due to the coverage of green oil, leading to deviations in test results.
Innovation Solution
A method involving the formation of a test structure with a second wafer having a completely retained top metal layer, used as a reference for the electrical performance of a first wafer, where bumps are formed on both wafers using electroplating and the same packaging process, enhancing the short-circuiting effect and contact performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder is added to the bump area for short-circuiting, then the electrical performance test can be conducted, but the green oil coverage causes poor short-circuiting effect and test result deviations
Solution Approach 1:
The patent creates a test structure that copies the essential features of the actual chip structure (bumps, metal layers, packaging) but uses a modified configuration where the top metal layer is completely retained and exposed. This copy allows testing of electrical performance without the interference of green oil, while still representing the actual product structure accurately enough to provide valid test data.
Solution Approach 2:
The test structure uses different metal layer configurations in different areas: the first die has the top metal layer removed (matching production), while the second die retains the complete top metal layer (for testing). This local differentiation allows each structure to serve its specific purpose optimally - production die for manufacturing and test die for accurate electrical performance measurement.
2Measurement precision
If the top metal layer is removed in the first wafer but completely retained in the second wafer, then the test structure provides better contact performance, but additional process steps are required
Solution Approach 1:
The patent divides the wafer into two separate wafers (first wafer for production, second wafer for testing) rather than trying to create different structures on the same wafer. This segmentation allows each wafer to be processed independently with appropriate metal layer handling, simplifying the overall process despite the additional wafer. The segmentation enables parallel processing and reduces cross-contamination risks.
Solution Approach 2:
The test structure is prepared in advance with the complete top metal layer retained before packaging. This preliminary preparation ensures that when testing is performed, the optimal contact conditions are already in place, eliminating the need for additional metal layer removal steps during the testing phase and reducing overall process complexity.
3Reliability
If a test structure with completely retained top metal layer is used, then test reliability is improved, but the device structure becomes more complex
Solution Approach 1:
The test structure creates a simplified copy of the production structure that retains only the essential elements needed for electrical performance testing (substrate, bumps, metal layers, packaging) while omitting non-essential elements (green oil coverage, circuit functionality). This copying approach achieves high test reliability without the full complexity of a complete functional chip.
Solution Approach 2:
The second wafer with the complete top metal layer serves multiple functions: it acts as both a test structure for electrical performance measurement and a reference structure for comparing against the first die. This multi-functionality reduces the need for separate reference structures, simplifying the overall system despite the retained metal layer complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and accuracy of electrical performance testing by ensuring better contact between the bumps and probes, reducing test cost and maintaining the same metal layer and packaging processes as the product wafers.
Implementation Method 1
forming bumps on the exposed part of the top metal layer by an electroplating process
Implementation Method 2
the top metal layer is formed by a sputtering process
Data Source
AI summary
A method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.