Packaged Fast Inverse Diode for PFC Boost Converter
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Solution Overview
Problem
Existing power diodes with high reverse breakdown voltage capabilities often lack dynamic robustness and efficient reverse recovery characteristics, limiting their application in high-current and high-voltage conditions.
Innovation Solution
A four-terminal packaged semiconductor device incorporating a fast recovery inverse diode with a P-type isolation structure and a P+ type charge carrier extraction region, which reduces charge carrier concentrations and eliminates the need for recombination centers, enabling low forward voltage drop, low peak reverse recovery current, high reverse breakdown voltage, and low reverse leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional power diodes with high reverse breakdown voltage are used, then high voltage capability is achieved, but dynamic robustness and reverse recovery characteristics deteriorate
Solution Approach 1:
The patent inverts the conventional diode structure by placing the P-type region on the bottomside instead of the topside. This inverse diode configuration with bottomside P-type anode region and topside N-type cathode region fundamentally changes the electric field distribution and charge carrier extraction mechanism, enabling simultaneous achievement of high reverse breakdown voltage and superior dynamic robustness
Solution Approach 2:
The patent introduces P-type peripheral sidewall diffusion regions that locally modify the electric field distribution at critical stress points. These localized P-type regions provide field termination and charge extraction at the periphery, improving dynamic robustness without compromising the overall high voltage blocking capability of the device
2Ease of manufacture
If conventional diode structures are used, then manufacturing simplicity is maintained, but reverse recovery current and forward voltage drop increase
Solution Approach 1:
The patent changes the spatial parameters of the diode structure by inverting the location of P-type and N-type regions. This parameter change in the structural configuration leads to improved charge carrier extraction efficiency, reducing forward voltage drop and reverse recovery current while maintaining manufacturing feasibility through standard semiconductor processing techniques
3Reliability
If inverse diode architecture is implemented, then dynamic robustness and reverse breakdown voltage are improved, but device complexity increases
Solution Approach 1:
The patent segments the isolation function into distinct components: bottomside P-type isolation regions, P-type peripheral sidewall diffusion regions, and N-type depletion stopper regions. This segmentation allows each region to perform its specific function efficiently, achieving superior dynamic robustness while maintaining a systematic and manufacturable structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a low forward voltage drop, low peak reverse recovery current, high reverse breakdown voltage, and low reverse leakage current, making it suitable for applications like 400 volt DC output voltage PFC boost converter circuits with improved dynamic ruggedness and efficiency.
Implementation Method 1
P+ type charge carrier extraction regions that extends downward from the top semiconductor surface and into the N type depletion stopper region
Data Source
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AI summary
A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.