Electronic Packaging Structure with Stress Buffering
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Solution Overview
Problem
Existing semiconductor packaging technologies face reliability issues due to mechanical and thermal stress, which weaken the bonding between the semiconductor wafer and the bonding layer, leading to potential cracking.
Innovation Solution
An electronic packaging structure that includes a substrate, a conductive layer, a stress buffering material, and an intermetallic compound, where the intermetallic compound is strategically positioned between the electronic device and the conductive layer, as well as between the substrate and the stress buffering material, to enhance stress buffering and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding packaging technique is used to electrically connect electrodes to wiring layer, then electrical connectivity is achieved, but mechanical strength and reliability are reduced due to thermal stress and creep effect at high temperatures
Solution Approach 1:
The patent introduces a stress buffering material layer between the semiconductor wafer and the package substrate that acts as an intermediary to absorb and distribute thermal and mechanical stress. This mediator prevents direct stress transmission to the bonding interface, thereby maintaining bonding reliability under high temperature conditions while preserving mechanical strength.
2Reliability
If semiconductor wafer is bonded with bonding layer at high temperatures, then electrical connection is established, but thermal stress weakens the bonding ability between wafer and bonding layer
Solution Approach 1:
The patent applies stress buffering material beforehand at the bonding interface to cushion against upcoming thermal stress during high-temperature operation. This pre-positioned cushioning layer absorbs expansion forces before they can damage the bonding interface, maintaining bonding ability despite thermal stress exposure.
3Reliability
If conventional packaging structure is used without stress buffering, then device complexity is low, but cracking occurs at bonding position of outer edge due to mechanical stress
Solution Approach 1:
The patent segments the packaging structure by introducing a distinct stress buffering material layer separate from the semiconductor wafer and package substrate. This segmentation allows the stress buffering layer to independently manage mechanical stress without complicating the overall device architecture, preventing cracking while maintaining structural clarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces stress transmission to the electronic device, enhancing its mechanical strength and reliability by using a stress buffering material and intermetallic compounds to manage thermal and mechanical stress.
Implementation Method 1
The intermetallic compound disposed between the electronic device and the conductive layer has a first thickness. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is a second thickness. The second thickness is greater than the first thickness.
Data Source
AI summary
An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.