Packaging Substrate Fabrication Using Metal Boards with Rectangular Openings

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Solution Overview

Problem

Conventional coreless packaging substrates require two electroplating processes, leading to high fabrication costs, and the carrier-free semiconductor packages face issues with encapsulant cracking and delamination due to bell-shaped conductive pillars formed by etching.

Innovation Solution

A packaging substrate with metal boards having openings on both surfaces, filled with encapsulants to define core circuit layers, eliminating the need for electroplating and reducing encapsulant cracking through perpendicular interfaces and protruding core circuit layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two electroplating processes are used to form conductive layers, then electrical conductivity is improved, but fabrication cost increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the electroplating process from the fabrication method by using pre-formed metal boards with conductive patterns instead of forming conductive layers through electroplating. This eliminates the need for electroplating while maintaining electrical conductivity through the metal board's inherent conductive structures.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of building up conductive layers through electroplating on a non-conductive substrate, the patent inverts the approach by using a metal board as the base substrate that inherently provides conductivity, eliminating the need for additive conductive layer formation.

Inventive Principle:
Principle #13The other way round (Inversion)

2Device complexity

If etching is used to form conductive pillars, then device complexity is reduced, but encapsulant cracking occurs due to bell-shaped geometry

Engineering Contradiction:
Improvestructure simplicityVSAvoidencapsulant integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the openings from bell-shaped to substantially rectangular with uniform cross-sections. This parameter change prevents stress concentration that causes encapsulant cracking while maintaining the simplified structure achieved through etching.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent designs the openings with uniform cross-sections and appropriate dimensions beforehand to prevent stress concentration during thermal cycling. This preemptive design prevents encapsulant cracking before it can occur during operation or testing.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Length of stationary object

If coreless packaging substrate is used, then thickness is reduced, but manufacturing precision becomes more difficult

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidalignment precision
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent uses pre-formed metal boards with pre-defined conductive patterns and openings. This preliminary preparation of the substrate with precise features before assembly simplifies the overall manufacturing process and maintains high precision without requiring complex alignment procedures during assembly.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9165789B2Fabrication method of packaging substrate
Publication Date: 2015.10.20 SILICONWARE PRECISION IND CO LTD
  • US9165789B2 patent drawing
  • US9165789B2 patent drawing
  • US9165789B2 patent drawing

AI summary

A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.