Packaging Substrate With Electroless NiPdAu Layer For Fine Pitch

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Solution Overview

Problem

Conventional semiconductor packaging substrates face challenges with fine-pitch applications due to reduced bonding areas, copper migration, surface treatment layer issues, and poor attachment of solder bumps and conductive wires, leading to reliability concerns and difficulties in meeting lead-free soldering requirements.

Innovation Solution

A packaging substrate with an electroless Ni/Pd/Au layer and copper bumps, where the palladium material acts as a catalyst for metal deposition, and recess portions are incorporated to alleviate stress and improve evenness, preventing copper migration and detachment, and facilitating fine-pitch applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the pitch between pads is continuously decreased to achieve finer packaging, then the bonding area between pads and solder bumps/balls is reduced, but this leads to poor attachment and reduced electrical connection reliability

Engineering Contradiction:
Improvepitch between padsVSAvoidelectrical connection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies different surface treatment layers to different pad types based on their specific requirements. Flip-chip pads receive an electroless Ni/Pd/Au layer optimized for solder bump attachment, while wire bonding pads receive an electroplated Ni/Au layer optimized for wire attachment. This local differentiation allows each pad type to achieve optimal bonding performance despite reduced pitch dimensions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite surface treatment structures combining multiple metal layers (electroless Ni/Pd/Au for flip-chip pads, electroplated Ni/Au for wire bonding pads) to achieve both strong attachment and electrical conductivity. The multi-layer composite structure provides enhanced bonding area and mechanical strength while maintaining electrical connection reliability in fine-pitch applications.

Inventive Principle:
Principle #40Composite materials

2Strength

If conventional electroplated Ni/Au surface treatment layers are used on flip-chip solder pads, then the attachment of solder bumps is poor, but switching to other materials may cause copper migration and short circuits

Engineering Contradiction:
Improveattachment strength of solder bumpsVSAvoidcopper migration causing short circuits
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an electroless Ni/Pd/Au surface treatment layer as an intermediary between the copper pad and solder bumps. The electroless Ni layer provides strong metallurgical bonding to solder bumps, the Pd layer prevents copper migration and acts as a diffusion barrier, and the Au layer provides corrosion resistance and solderability. This intermediary layering structure simultaneously achieves strong attachment and prevents harmful copper migration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The electroless Ni/Pd/Au composite surface treatment layer combines multiple materials with complementary properties: Ni for strong bonding, Pd for migration prevention, and Au for corrosion resistance. This composite structure resolves the contradiction between achieving strong solder bump attachment and preventing copper migration-induced short circuits.

Inventive Principle:
Principle #40Composite materials

3Strength

If conventional electroplated Ni/Au surface treatment layers are used on wire bonding pads, then the attachment of conductive wires is poor, but improving the surface treatment may affect fine-pitch applications

Engineering Contradiction:
Improveattachment strength of conductive wiresVSAvoidevenness for fine-pitch applications
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent applies electroplated Ni/Au surface treatment specifically to wire bonding pads, which have larger dimensions and do not require the same level of fine-pitch precision as flip-chip pads. The electroplating process provides excellent wire attachment strength through metallurgical bonding while the controlled plating thickness maintains surface evenness suitable for wire bonding operations.

Inventive Principle:
Principle #3Local quality

4Manufacturing precision

If the exposed area of pads is reduced due to smaller opening diameters, then fine-pitch applications are enabled, but the bonding area for solder bumps and balls is insufficient

Engineering Contradiction:
Improvefine-pitch capabilityVSAvoidbonding area of pads
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent uses electroless Ni/Pd/Au composite surface treatment on flip-chip pads to maximize bonding area within constrained dimensions. The electroless plating process provides uniform thin layers that conform to pad geometry, creating effective bonding surfaces even when pad exposed areas are small. The multi-layer composite structure increases the effective bonding interface area through metallurgical interlocking.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The electroless Ni/Pd/Au layer enhances electrical connection reliability by preventing short circuits, ensuring evenness for fine-pitch applications, and improving wire bonding processes, while the recess portions reduce stress and enhance coplanarity, addressing the limitations of conventional surface treatment layers.

Implementation Method 1

an electroless Ni/Pd/Au layer disposed on the first bumps and the wire bonding pads

Methodology Applied
Scientific EffectElectroless plating: Electroplating

Implementation Method 2

the palladium material acts as a catalyst for metal deposition

Methodology Applied
Scientific EffectCatalysis: Catalysis

Data Source

PatentUS7812460B2Packaging substrate and method for fabricating the same
Publication Date: 2010.10.12 UNIMICRON TECH CORP
  • US7812460B2 patent drawing
  • US7812460B2 patent drawing
  • US7812460B2 patent drawing

AI summary

A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications.