Packed Fin Transistor Layout With Low-Parasitic Source/Drain Contacts
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Solution Overview
Problem
The challenge in semiconductor die design is to reduce the area of transistors while minimizing the increase in parasitic resistance and capacitance, which is often compromised by the layout of transistors that need to balance area savings with resistance and capacitance reduction.
Innovation Solution
The design incorporates fins with source/drain contact layers and metal layers that do not overlap the fins, along with rectangular vias that reduce parasitic resistance, allowing the active region to be moved closer to the gate metal layer, thereby reducing the transistor area without significant increases in parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transistor layout is optimized to reduce area, then the area of each transistor is reduced, but parasitic resistance and/or parasitic capacitance increases
Solution Approach 1:
The source and drain regions are segmented into multiple discrete contact layers (first source contact layer, second source contact layer, first drain contact layer, second drain contact layer) rather than using single continuous contacts. This segmentation allows for optimized current distribution and reduced parasitic resistance while maintaining compact area
Solution Approach 2:
The patent introduces multiple vertical layers (contact layers, metal layers) to reduce parasitic resistance, moving the solution from a 2D plane optimization to a 3D vertical stacking approach. The first and second contact layers are positioned at different vertical levels, creating additional current paths that reduce resistance without increasing planar area
2Area of stationary object
If the transistor layout is optimized to reduce area, then the area of each transistor is reduced, but parasitic capacitance increases
Solution Approach 1:
The gate contact is segmented into first and second gate contact layers positioned at different vertical levels, with the first gate contact layer adjacent to the first gate and the second gate contact layer adjacent to the second gate. This segmentation reduces parasitic capacitance by distributing the capacitive coupling across multiple separated interfaces rather than a single large interface
Solution Approach 2:
Insulating layers are introduced as intermediary elements between conductive layers that would otherwise be in direct contact. These insulating layers reduce parasitic capacitance by providing electrical isolation while maintaining structural integrity and allowing for continued current flow through vertical vias
3Device complexity
If source/drain metal layers overlap fins, then electrical connection is simplified, but parasitic resistance increases
Solution Approach 1:
The patent resolves the overlap conflict by moving to a 3D vertical arrangement where metal layers and fins occupy different vertical levels. Vias provide vertical electrical connections between layers, eliminating the need for horizontal overlap while maintaining low resistance through direct vertical contact paths
Solution Approach 2:
Vias serve as intermediary connection elements that bridge the gap between metal layers and fins without requiring overlap. These vertical conductive structures provide direct electrical pathways through the insulating layers, reducing parasitic resistance while simplifying the lateral layout
Data Source
AI summary
A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.