Microprocessor Instruction Decoding with Packed Operand Lookup
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In microprocessors, executing computer instructions with complex arithmetic operations, such as those involving packed operands, is inefficient due to the need for out-of-order execution of multiple micro-operations, which prolongs the completion time.
Innovation Solution
A method and apparatus that decode computer instructions into micro-instructions with packed operands, generating addresses to read approximations from a lookup table, optimizing the execution process by reducing the number of stages required to complete operations, specifically using a Decoding Unit, ROM, ROM controller, address generator, and controller to direct the generation of addresses for reciprocal approximations of SPFP or DPFP values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a computer instruction with packed operand is decoded into multiple micro-operations for out-of-order execution, then the microprocessor can execute instructions in parallel, but the execution time is prolonged due to excessive number of micro-operations
Solution Approach 1:
The patent combines multiple micro-operations into a single micro-operation that processes all packed operands simultaneously. Instead of generating separate micro-operations for each operand, the invention creates one unified micro-operation that handles all n input parameters in parallel, reducing the total number of micro-operations and enabling faster instruction completion while maintaining out-of-order execution capability
Solution Approach 2:
The patent introduces a new dimension of parallelism by processing multiple operands within a single micro-operation through vectorized operations. The execution unit is designed to handle n input parameters simultaneously using a single instruction, effectively adding a dimension of operand-level parallelism without increasing the number of micro-operations
2Ease of operation
If multiple micro-operations are generated for complex arithmetic operations, then the operations can be broken down into basic steps, but the number of execution stages increases from five to seven stages
Solution Approach 1:
The patent merges multiple decomposition steps into a single unified micro-operation that performs complex arithmetic operations on all packed operands simultaneously. The execution unit integrates multiple functional capabilities (arithmetic operations, logical operations, data transfer) into one cohesive operation, reducing the pipeline stage count from seven to five while maintaining operational decomposability
3Speed
If a lookup table is used to store approximations for all possible input values, then the execution speed is improved, but the memory size and device complexity increase
Solution Approach 1:
The patent segments the lookup table into multiple smaller tables, each handling a specific range or type of input values. This segmentation allows the system to maintain fast lookup performance while reducing the size of individual tables and enabling selective access based on input characteristics, thereby lowering overall device complexity
Solution Approach 2:
The patent optimizes the lookup table structure by organizing data in a multi-dimensional format that allows efficient access patterns. By changing the organization dimension of the lookup table, the system achieves fast retrieval performance with reduced memory requirements through compact storage layouts
Data Source
AI summary
The invention introduces a method for executing a computer instruction, which contains at least the following steps: decoding the computer instruction to generate a micro-instruction at least containing an opcode (operation code) and a packed operand, where the packed operand contains all n input parameters corresponding to the computer instruction; generating n addresses of the n input parameters according to the opcode and the packed operand; and reading n approximations corresponding to the n addresses from a lookup table.