Intelligent Packet Aggregation via Dynamic Queue Coordination

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Solution Overview

Problem

Current network card technologies face inefficiencies in packet processing, leading to reduced throughput as network demands increase, due to factors like CPU overhead, cache misses, and inadequate utilization of parallel processing capabilities.

Innovation Solution

Implementing an intelligent packet aggregation method using a network interface device (NID) that offloads tasks from the CPU to co-processors like GPUs, ASICs, and FPGAs, and employs dynamic packet scheduling and prioritization based on environmental states and time-division multiplexing to optimize packet processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional network card packet processing is used, then CPU can process packets, but throughput decreases and system bottlenecks increase as network demands grow

Engineering Contradiction:

Improvepacket processing throughputVSAvoidCPU overhead and processing burden

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The packet processing system is segmented into multiple independent processing elements (PEs) that can operate in parallel. Each PE handles specific packet processing tasks, distributing the CPU workload and enabling concurrent packet processing, thus increasing throughput while reducing single-CPU overhead

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A coordinator circuit is introduced as an intermediary between the network interface device and multiple processing elements. This coordinator manages packet distribution to appropriate PEs based on packet characteristics and processing element availability, optimizing the processing workflow without increasing CPU burden

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If more processing elements are added to increase parallelism, then packet processing speed improves, but device complexity increases

Engineering Contradiction:

Improvepacket processing speedVSAvoidnumber of processing elements and coordination mechanisms

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Processing elements are designed with universal functionality to handle multiple packet processing tasks. Each PE can process different packet types and perform various operations (routing, switching, protocol handling), maximizing the utility of each added element and reducing the total number of specialized components needed

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically assigns packets to processing elements based on real-time conditions such as packet characteristics, PE availability, and processing priorities. This dynamic scheduling optimizes throughput while managing complexity through adaptive rather than static resource allocation

Inventive Principle:

Principle #15Dynamics

3Productivity

If packets are processed individually, then processing simplicity is maintained, but cache misses increase and processing efficiency decreases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidcache misses

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

Multiple packets are merged into batches and processed together by processing elements. This batch processing approach improves cache utilization by reducing the number of cache misses compared to individual packet processing, while also enabling better optimization of processing operations

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Packet processing parameters and data are prepared and loaded into processing elements in advance before actual packet processing occurs. This preliminary action ensures that processing elements have all necessary information and resources ready, reducing cache misses and optimizing processing efficiency

Inventive Principle:

Principle #10Preliminary action

4Productivity

If dynamic packet scheduling based on environmental states is implemented, then network throughput improves, but control complexity increases

Engineering Contradiction:

Improvenetwork throughputVSAvoidscheduling control mechanisms

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system continuously monitors environmental states such as network traffic conditions, processing element status, and queue depths. This feedback information is used to dynamically adjust packet scheduling decisions, optimizing throughput through adaptive control based on real-time system conditions

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The packet processing system autonomously makes scheduling decisions based on packet characteristics and current system state without requiring external CPU intervention. The coordinator circuit self-manages packet distribution to processing elements, reducing control complexity by eliminating the need for complex external scheduling mechanisms

Inventive Principle:

Principle #25Self-service

Data Source

PatentEP3563533B1Intelligent packet aggregation

Publication Date: 2022.03.02 INTEL CORP

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AI summary

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.