Packet Aggregation Engine for Lower-Overhead CPU Processing
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Solution Overview
Problem
Existing packet processing techniques, such as LRO and GRO, face inefficiencies due to CPU overhead, memory bandwidth limitations, and limited configurability, leading to suboptimal performance in both hardware and software-based optimizations.
Innovation Solution
A system utilizing hardware to store data packets in an internal memory and firmware to aggregate them into an external memory based on flow and segment numbers, creating an aggregated data packet for efficient processing by a CPU, combining the benefits of hardware and software flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based packet aggregation (GRO) is used, then flexibility and configurability are improved, but CPU overhead and processing time increase
Solution Approach 1:
The patent introduces a dedicated packet aggregation engine as an intermediary component between the network interface and CPU. This engine operates independently from the CPU, using hardware-accelerated packet aggregation techniques while maintaining software-like configurability through programmable parameters. The intermediary handles packet buffering, segmentation, and reassembly operations, freeing the CPU from these time-consuming tasks while preserving flexibility through configurable aggregation rules.
Solution Approach 2:
The patent replaces software-based packet aggregation mechanisms with hardware-accelerated processing. By implementing packet aggregation logic in dedicated hardware circuits rather than software routines, the system achieves faster processing speeds while maintaining configurability through hardware programmability. This substitution eliminates the CPU overhead associated with software-based GRO while preserving adaptability through programmable aggregation parameters.
2Speed
If hardware-based packet aggregation is used, then processing speed is improved, but device complexity and memory bandwidth requirements increase
Solution Approach 1:
The patent divides the packet aggregation function into distinct modular components: a packet reception module, an aggregation engine with separate buffering and processing units, and a transmission module. Each component handles specific aspects of packet aggregation independently, reducing overall device complexity through functional decomposition. The segmentation allows hardware acceleration while maintaining manageable complexity through clear separation of concerns.
Solution Approach 2:
The patent implements a nested architecture where the packet aggregation engine is integrated within the network interface controller, which itself is part of the larger communication system. The aggregation engine contains nested sub-components including packet buffers, segmentation units, and reassembly modules. This nesting allows hardware acceleration while containing complexity within hierarchical boundaries, making the overall system more manageable.
3Adaptability or versatility
If multiple memory accesses are performed for packet aggregation, then aggregation flexibility is improved, but memory bandwidth consumption increases
Solution Approach 1:
The patent combines multiple packet data streams into a single aggregated data stream using dedicated buffering memory within the packet aggregation engine. By merging packets belonging to the same flow into consolidated buffers, the system reduces the number of separate memory access operations required. This combining approach maintains aggregation flexibility while minimizing memory bandwidth consumption through efficient data consolidation.
Solution Approach 2:
The patent performs preliminary packet buffering and organization in dedicated memory structures before aggregation processing. Packets are pre-sorted and staged in buffer memory based on their aggregation criteria, allowing the aggregation engine to process them efficiently in batches. This preliminary action reduces the need for repeated memory accesses during aggregation, maintaining flexibility while conserving memory bandwidth.
Data Source
AI summary
A method may include obtaining, by a hardware, multiple data packets. The method may also include storing, by the hardware, the multiple data packets in an internal memory. The method may further include allocating, by a firmware, a contiguous portion of external memory. The method may also include determining, by the firmware, a particular flow and a segment number associated with individual data packets of the multiple data packets. The method may further include storing, by the firmware, the individual data packets in the external memory to create an aggregated data packet. The storing may be based on the particular flow and the segment number. The method may also include transmitting, by the firmware, the aggregated data packet to a host CPU for processing.