Packet Buffer Clock Control for Power Reduction
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Solution Overview
Problem
Packet communication devices face high power consumption due to constant clock signal supply even when no packet processing is required, leading to increased standby power consumption and reduced throughput during low traffic periods.
Innovation Solution
A packet processing apparatus that includes a clock control unit that measures the time when no packet data is accumulated in the buffer and adjusts the clock signal supply accordingly, either suspending it or reducing its frequency, to minimize power consumption without affecting data processing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signal is constantly supplied to packet processing unit, then data processing throughput is maintained, but power consumption increases significantly during low traffic periods
Solution Approach 1:
The patent applies dynamics by making the clock signal supply adjustable rather than fixed. The clock control unit dynamically changes the clock supply state based on buffer occupancy detection - providing full clock signals when packets are present and suspending or reducing clock supply when the buffer is empty, thereby adapting the system state to actual workload conditions
Solution Approach 2:
The patent implements feedback through the buffer occupancy detection unit that continuously monitors packet buffer status and provides information to the clock control unit. This feedback loop enables the system to automatically adjust clock supply based on real-time packet processing needs, resolving the contradiction between maintaining throughput and reducing power consumption
2Use of energy by moving object
If clock signal supply is suspended when no packet data is present, then power consumption is reduced, but data processing throughput may be affected
Solution Approach 1:
The patent applies preliminary action by having the buffer occupancy detection unit continuously monitor packet buffer status before clock supply suspension occurs. This advance detection allows the system to prepare for potential packet arrivals and ensure that clock supply can be quickly restored when needed, preventing throughput degradation while maintaining power savings
3Use of energy by moving object
If asynchronous circuit configuration is adopted, then power consumption is reduced in both normal operation and standby state, but development tools and verification capabilities are insufficient
Solution Approach 1:
The patent applies parameter changes by modifying the operational parameters of the clock signal based on buffer occupancy conditions. Instead of adopting a completely asynchronous configuration, the system changes clock supply parameters (frequency, presence/absence) dynamically based on actual packet processing needs, achieving power reduction while maintaining compatibility with existing synchronous design tools and methodologies
Data Source
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AI summary
A packet processing apparatus includes a packet buffer unit that temporarily holds packet data, a packet processing unit that processes packet data output from the packet buffer unit, a clock supply unit that supplies a clock signal to the packet processing unit, and a control unit that detects a buffer vacant time indicating a time during which no packet data exists in the packet buffer unit based on an accumulation amount of the packet data in the packet buffer unit, and controls an operational state of the clock supply unit in accordance with the buffer vacant time.