Packet Buffering and Flushing for Network Processor Scalability
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Solution Overview
Problem
High-speed networking equipment faces bottlenecks in packet diversion and insertion due to the use of ingress/egress points for host processors, leading to reduced bandwidth and scalability issues as networking speeds increase, especially when handling multiple datacom and telecom protocols.
Innovation Solution
A buffering structure with storage structures and associated packet diversion and insertion logic that facilitates post-switching, pre-medium placement diversion and/or insertion of egress packets, and post-medium extraction, pre-switching diversion and/or insertion of ingress packets, with selective tail and head flushing capabilities, allowing for efficient packet management without consuming ingress/egress points, thus supporting multiple datacom and telecom protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If host processors are coupled to ingress/egress points for packet diversion and insertion, then packet processing functionality is achieved, but bandwidth is reduced and scalability is limited
Solution Approach 1:
The patent extracts the packet buffering and diversion functionality from the ingress/egress points and places it in dedicated buffer memory structures within the switching fabric. This separation allows the ingress/egress points to focus on high-speed packet forwarding while the buffers handle diversion and insertion operations, thereby preserving bandwidth and improving scalability.
Solution Approach 2:
The patent introduces buffer memory structures as intermediary components between the switching fabric and host processors. These buffers act as mediators that enable packet diversion and insertion without requiring host processors to be directly coupled to ingress/egress points, thus maintaining high bandwidth while providing the required functionality.
2Adaptability or versatility
If multiple host processors are employed to increase packet processing capacity, then diversion and insertion capability is improved, but ingress/egress points are consumed and bandwidth is reduced
Solution Approach 1:
The patent creates universal buffer memory structures that can serve multiple packet processing functions (diversion, insertion, buffering) without requiring dedicated ingress/egress points for each host processor. This multi-functional approach allows multiple processors to share the same physical interfaces, improving capacity while conserving bandwidth.
3Productivity
If packet buffering is implemented to enable diversion and insertion, then packet management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the buffering structure into multiple independent buffer memory structures, each associated with specific ingress or egress points. This segmentation allows for modular design and management, improving packet management efficiency while keeping the complexity of each individual buffer manageable. The buffers can be independently controlled and flushed based on specific protocol requirements.
Data Source
AI summary
A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.