Packet Buffer Memory With Package Descriptors For DRAM Scheduling

The patent segments the buffer memory into multiple queues, where each queue is managed independently with its own head and tail pointers. This segmentation allows the system to serve multiple traffic flows simultaneously through parallel access patterns, effectively masking the slow access time of DRAM and enabling high bit rate operation without requiring expensive SRAM.

The patent implements dynamic queue management where the buffer allocates memory space to queues based on actual traffic demand rather than static pre-allocation. The queue manager dynamically adjusts the head and tail positions within the DRAM buffer, allowing the system to achieve SRAM-like responsiveness for active queues while maintaining the cost and power efficiency of DRAM for the overall buffer structure.

The patent allows queues to exceed their allocated portion of the buffer when sufficient memory space is available, implementing elastic sharing. The queue manager monitors buffer utilization and permits queues to expand into unused space dynamically, ensuring that high-priority queues can utilize more buffer space when needed while maintaining isolation guarantees when the buffer is full.

The patent implements a queue manager that performs preliminary actions by pre-positioning packet data and maintaining ready queues in DRAM before transmission is needed. The system pre-allocates buffer spaces and prepares packet sequences in advance, so that when line-rate transmission is required, the data is already positioned for immediate sequential access, eliminating the need for slow random access operations during critical transmission windows.