Packet Buffer Spill-Over for Network Devices
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Solution Overview
Problem
Network devices face challenges in buffering packets due to the mismatch between internal and external packet memory bandwidths, where internal memories have higher access bandwidths but lower storage capacity, and external memories have lower access bandwidths that cannot support full network device bandwidths during congestion.
Innovation Solution
A network device architecture that utilizes both internal and external packet memories, where packets are initially buffered in internal memory and selectively transferred to external memory during congestion, maintaining packet order and reducing bandwidth requirements for external memories, allowing efficient use of larger external buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external packet memory is used to increase storage capacity, then storage capacity is improved, but access bandwidth is reduced
Solution Approach 1:
The patent divides the packet memory system into two segments: internal packet memory for high-bandwidth access and external packet memory for large storage capacity. The packet processor selectively transfers packets between these segments based on congestion conditions, allowing each segment to operate in its optimal performance zone.
Solution Approach 2:
The system dynamically adjusts the distribution of packets between internal and external memory based on real-time congestion detection. When congestion is detected in internal memory, the system activates spill-over to external memory; when internal memory has available capacity, packets are kept there for faster access.
2Speed
If internal packet memory is used to maintain high access bandwidth, then access bandwidth is improved, but storage capacity is reduced
Solution Approach 1:
The patent merges internal and external packet memories into a unified buffering system. The packet processor manages both memory types as a single logical buffer, transferring packets between them as needed to balance bandwidth requirements and storage capacity constraints.
Solution Approach 2:
The packet processor acts as an intermediary between internal and external memory, controlling packet flow between them. It detects congestion in internal memory and selectively forwards packets to external memory, effectively mediating the trade-off between bandwidth and capacity.
3Speed
If external packet memory bandwidth is increased to support full network device bandwidth, then access bandwidth is improved, but cost and complexity increase
Solution Approach 1:
The patent applies partial action by having external memory handle only the overflow portion of packet buffering during congestion, rather than requiring it to support the full network device bandwidth. This reduces the bandwidth requirements and complexity of the external memory system.
Data Source
AI summary
A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.