Internal External Memory Packet Byte Counting Overflow Handling
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Solution Overview
Problem
Network devices, such as switches, face limitations in processing and access speed when counting packets and bytes, leading to constrained counting capabilities due to the technical limitations of existing hardware.
Innovation Solution
A system utilizing both internal and external memory, where an internal memory with limited bits is used to store subtotals of packets and bytes, and an external memory updates totals when the internal memory overflows, optimizing bit allocation and handling high packet rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware counters are used to count packets and bytes, then counting capability is provided, but processing and access speed limitations constrain the counting capability
Solution Approach 1:
The counter is divided into two separate memory components: internal memory for storing packet counts and external memory for storing byte counts. This segmentation allows each memory type to be optimized for its specific function, with internal memory providing fast access for packet counting and external memory providing sufficient capacity for byte counting, thereby resolving the speed-capability contradiction.
2Reliability
If more bits are allocated to internal memory counters, then more packets and bytes can be counted, but resource expenditure increases excessively
Solution Approach 1:
The solution transitions from a single-dimension internal memory counter to a two-dimensional architecture combining internal and external memory. This dimensional expansion allows the system to achieve extended counting range without proportionally increasing internal memory resources, as external memory provides the additional storage capacity needed for high-volume byte counting.
Data Source
AI summary
Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.