Packet and Byte Counting Using Split Memory Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Network devices face challenges in efficiently counting packets and bytes due to processing speed limitations in existing hardware, which restricts their counting capabilities, especially when handling high packet rates.
Innovation Solution
A network device system utilizing both fast and slow memories, where the fast memory stores the least significant bit (LSb) portion of a count value and the slow memory stores the most significant bit (MSb) portion, with update circuitry that increments or decrements the LSb upon events and the MSb upon wrap-around events, allowing for accurate and efficient counting without frequent access to slow memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional hardware counters are used to count packets and bytes, then the counting function is provided, but the processing speed is limited and cannot handle high packet rates
Solution Approach 1:
The counter is segmented into two separate memory components: a first memory (fast memory) storing the least significant bits (LSBs) of the count value, and a second memory (slow memory) storing the most significant bits (MSBs). This segmentation allows the system to utilize the high-speed access of the first memory for frequent packet counting operations while the second memory handles less frequent updates, thereby resolving the contradiction between counting speed and packet handling capability.
2Speed
If fast memory is used to store the entire count value, then counting speed is improved, but memory cost and complexity increase
Solution Approach 1:
Different portions of the count value are stored in memories with different performance characteristics. The least significant bits, which change frequently, are stored in fast memory for quick access. The most significant bits, which change less frequently, are stored in slower, more cost-effective memory. This local quality differentiation optimizes the overall system by matching memory speed to the actual access requirements of each data portion, improving access speed while controlling complexity.
Solution Approach 2:
The count value is divided into two segments: LSBs stored in fast memory and MSBs stored in slow memory. This segmentation allows the system to use smaller, cheaper fast memory for the frequently accessed LSBs while using larger, slower memory for the MSBs, thereby reducing overall memory cost and complexity while maintaining high access speed for critical counting operations.
3Quantity of substance
If the entire count value is stored in slow memory, then memory cost is reduced, but access speed becomes insufficient for high packet rates
Solution Approach 1:
The count value is segmented such that the LSBs (which require frequent access for packet counting) are stored in fast memory, while the MSBs are stored in slow memory. This segmentation ensures that the most frequently accessed data resides in high-speed memory, maintaining adequate access speed for high packet rates, while the majority of the memory capacity can be allocated to the slower, cheaper memory for storing MSBs and other data.
Solution Approach 2:
The system applies local quality by storing different portions of the count value in memories with different speed characteristics. The LSBs, which need fast access, are placed in fast memory, while the MSBs can be stored in slower memory. This approach allows the system to use more slow memory (reducing cost) while ensuring that the critical LSB access operations remain fast enough for high packet rates.
Data Source
AI summary
A network device and a method for maintaining a count of network events in a network device are provided. A first memory is configured as a first counter, where the first counter is configured to store a least significant bit (LSb) portion of a count value. A second memory is configured as a second counter, where the second counter is configured to store a most significant bit (MSb) portion of the count value. Update circuitry is configured to (i) selectively increment or decrement the LSb portion of the count value stored in the first memory upon occurrence of an event, and (ii) selectively increment or decrement the MSb portion of the count value stored in the second memory upon occurrence of a wrap-around event in the first memory.