Packet Cache Eviction Control for SRAM-DRAM Buffering

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Solution Overview

Problem

Packet-based communication systems face challenges in efficiently managing and storing packets due to processing speed limitations, particularly when packets are received or transmitted faster than they can be acknowledged, necessitating temporary storage in cache memory to maintain high communication performance.

Innovation Solution

A packet cache system that includes a cache memory allocator, hash table, and eviction engine to manage efficient data transfer between on-chip SRAM and off-chip DRAM, ensuring transparent data storage and retrieval, and prioritizes packet eviction based on occupancy and priority.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If packets are stored in cache memory to maintain high communication performance, then speed is improved, but device complexity increases due to the need for cache management mechanisms

Engineering Contradiction:
Improvecommunication performanceVSAvoidcache management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The eviction engine automatically monitors cache occupancy and autonomously evicts packets from cache to non-cache memory when occupancy thresholds are exceeded, without requiring external intervention or complex control logic. The system self-regulates by comparing occupancy against thresholds and performing evictions independently

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system continuously monitors cache occupancy and uses this feedback to trigger eviction operations. When occupancy exceeds predefined thresholds, the eviction engine activates to reduce occupancy back within acceptable ranges, creating a closed-loop control system that maintains performance while managing complexity

Inventive Principle:
Principle #23Feedback

2Productivity

If cache memory occupancy is increased to store more packets, then productivity is improved, but reliability decreases due to potential data loss under congestion scenarios

Engineering Contradiction:
Improvepacket storage capacityVSAvoiddata management reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system pre-establishes occupancy thresholds and eviction policies before congestion occurs. When thresholds are approached, evictions are proactively performed to prevent overflow and data loss, rather than reacting after the problem occurs. This preliminary action maintains reliability while maximizing cache utilization

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cache management system dynamically adjusts between storing packets and evicting packets based on real-time occupancy conditions. The eviction engine activates or deactivates based on whether occupancy exceeds thresholds, creating a dynamic balance between maximizing storage capacity and maintaining data reliability

Inventive Principle:
Principle #15Dynamics

3Reliability

If eviction operations are performed frequently to maintain cache occupancy, then reliability is improved, but loss of time increases due to repeated data transfers

Engineering Contradiction:
Improvecache management reliabilityVSAvoideviction operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system uses occupancy thresholds as adjustable parameters to control when evictions occur. By tuning these threshold parameters, the system optimizes the balance between maintaining reliability through evictions and minimizing time loss by avoiding excessive eviction operations. The thresholds act as control parameters that regulate eviction frequency

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4465185B1Packet cache system and method
Publication Date: 2026.03.04 GOOGLE LLC
  • EP4465185B1 patent drawingFigure 1
  • EP4465185B1 patent drawingFigure 2
  • EP4465185B1 patent drawingFigure 3

AI summary

A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.