Packet Classification Using CPU and GPU Parallel Processing

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Solution Overview

Problem

Current software-based packet classification methods struggle to meet the high throughput requirements of modern communication networks, particularly in virtualized environments and software-defined networking, due to limitations in speed and scalability, especially when dealing with large rule tables and multi-dimensional tuples.

Innovation Solution

A packet classification system utilizing a primary CPU and secondary GPU processing unit, where the GPU processes tuples in parallel across distributed processing blocks to evaluate packet classification rules, enhancing speed and efficiency through accelerated processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If software-based packet classification is used to reduce cost and power consumption, then device cost and power consumption are reduced, but processing speed and throughput are insufficient to meet 10 Gbps requirements

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing throughput
Core Design Contradiction:
Use of energy by stationary objectVSProductivity

Solution Approach 1:

The patent segments the packet classification task into multiple independent processing blocks, each handling a specific portion of the classification rules. This allows parallel processing across multiple cores or processing units, significantly increasing throughput while keeping each individual processing unit power-efficient.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-threaded sequential processing to multi-dimensional parallel processing by organizing classification rules into multiple processing blocks that can execute simultaneously across different cores or processing units, adding a spatial dimension to the processing architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If TCAM hardware is used to achieve fast packet classification, then processing speed is improved, but device cost, storage capacity, and power consumption increase significantly

Engineering Contradiction:
Improveprocessing speedVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the specialized TCAM hardware mechanism with a software-based processing system that uses standard memory and general-purpose processors. This substitution maintains high processing speeds through parallelization while eliminating the complexity, cost, and power requirements of TCAM hardware.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If software-based packet classification is used to improve adaptability to virtualized environments, then system flexibility and adaptability are improved, but processing throughput cannot meet 10 Gbps requirements

Engineering Contradiction:
Improveenvironmental adaptabilityVSAvoidprocessing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent creates a universal packet classification system that can operate in various environments (physical switches, virtual switches, SDN controllers) by using standardized data structures and processing blocks. The same software architecture adapts to different deployment scenarios while maintaining high throughput through parallel processing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9509809B2Packet classification using multiple processing units
Publication Date: 2016.11.29 NOKIA OF AMERICA CORP
  • US9509809B2 patent drawing
  • US9509809B2 patent drawing
  • US9509809B2 patent drawing

AI summary

A packet classification capability is presented herein. The packet classification capability enables improvements in packet classification via use of a combination of a primary processing unit and a secondary processing unit where the secondary processing unit is configured to perform packet classification functions in parallel based on distribution of packet classification information across processing blocks of the secondary processing unit. The processing blocks of the secondary processing unit may be supported using a set of processing elements, where each of the processing elements may include a shared memory, respectively. The secondary processing unit may be configured to use a linear search process, a tuple search process, a Bloom search process, or the like. The primary processing unit may be a Central Processing Unit (CPU) and the secondary processing unit may be a Graphics Processing Unit (GPU).