Packet Classification Module Memory Optimization

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Solution Overview

Problem

Existing packet classification methods require large amounts of memory, leading to increased costs and performance issues due to memory access latency, as they rely on representing all possible values of packet fields in RAM, making it impractical to store databases on a single chip with the processor.

Innovation Solution

A method that classifies data packets based on a primary condition, using an action descriptor to determine if a secondary condition is satisfied, optimizing memory usage by evaluating conditions efficiently based on their type and implementing them using appropriate methods such as linked-node structures or hash functions, and integrating the packet classification module on a single semiconductor chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a database of packet fields is stored in RAM to enable packet classification, then classification functionality is achieved, but memory size and cost increase significantly

Engineering Contradiction:
Improvepacket classification functionalityVSAvoidmemory size
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments the classification database into multiple banks, where each bank stores a subset of classification entries. This allows parallel access to different portions of the database simultaneously, reducing the effective memory access time while maintaining comprehensive classification coverage. The segmentation also enables the database to be distributed across available memory resources without requiring a single large contiguous memory block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the database structure by organizing entries into multiple levels or tiers. Frequently accessed classification rules are placed in faster memory regions (closer to the processor), while less frequently accessed rules are stored in slower but larger memory regions. This dimensional organization optimizes the trade-off between access speed and storage capacity, reducing the effective memory size requirement for high-performance classification.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the database is stored off-chip from the processor, then memory capacity is sufficient, but memory access latency increases and performance decreases

Engineering Contradiction:
Improvememory capacityVSAvoidmemory access latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements a nested memory structure where smaller, faster memory banks are embedded within or alongside larger, slower memory structures. The classification database is organized such that commonly accessed entries reside in small, fast SRAM banks that can be accessed with minimal latency. These SRAM banks are nested within or adjacent to larger DRAM or off-chip memory that provides the necessary total capacity. This nesting allows the system to achieve both high-speed access for frequent operations and sufficient total capacity for comprehensive classification rules.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Adaptability or versatility

If all possible values of packet fields are represented in memory, then complete classification coverage is achieved, but hardware cost and size increase greatly

Engineering Contradiction:
Improveclassification coverageVSAvoidhardware size
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal classification engine that can handle multiple packet field types and classification criteria using the same hardware infrastructure. The database structure is designed to accommodate various packet fields (source IP, destination IP, port numbers, protocol types, etc.) in a unified format, allowing a single memory system to serve all classification needs. This multi-functionality reduces hardware duplication and optimizes the ratio of classification coverage to hardware size.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs parameter changes by dynamically adjusting the classification database structure based on traffic patterns and priority requirements. The system can reconfigure which packet fields are indexed and how entries are organized in memory based on observed traffic characteristics. This dynamic parameter adjustment allows the hardware to adapt to different classification scenarios without requiring physical reconfiguration, optimizing the coverage-to-size ratio for varying network conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8111697B1Methods and apparatus for packet classification based on multiple conditions
Publication Date: 2012.02.07 JUNIPER NETWORKS INC
  • US8111697B1 patent drawing
  • US8111697B1 patent drawing
  • US8111697B1 patent drawing

AI summary

In one embodiment, a method includes classifying a data packet received at a switch fabric, selecting an action descriptor in response to the classifying, and processing an action defined in the action descriptor. The classifying is based on a primary classification condition and first portion of the data packet. The action descriptor is associated with the primary classification condition. The processing includes determining whether a secondary classification condition is satisfied by a second portion of the data packet.