Packet Classification Table Management for PCIe Function Level Reset
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Solution Overview
Problem
Managing packet classification tables in multi-function I/O devices is challenging due to large table sizes and the need for quick sanitization during Function Level Resets (FLRs), which can cause dropped traffic or require expensive additional hardware.
Innovation Solution
Implementing management logic that includes a function enabler data structure and a gate array to track valid DMA engines, allowing packets destined for invalid functions to be dropped until table entries are cleared, and enabling rapid identification of affected entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If classification table entries are cleared sequentially during FLR, then data sanitization is achieved, but processing time exceeds the bounded period requirement
Solution Approach 1:
The patent applies preliminary action by setting a 'sanitized' bit in each classification table entry before actually clearing the data. This allows the system to mark entries as sanitized immediately when the FLR is initiated, rather than waiting to clear each entry sequentially. The actual data clearing can then proceed in the background without blocking the FLR completion, thus meeting the bounded time requirement while ensuring complete sanitization.
2Productivity
If a dedicated hardware walker is used to search and clear classification table entries, then FLR processing is accelerated, but device complexity and cost increase
Solution Approach 1:
The patent implements self-service by enabling the classification table hardware to automatically clear its own entries when the sanitized bit is set. Instead of requiring an external hardware walker to search and clear each entry, the classification table structure itself performs the clearing operation, eliminating the need for additional sophisticated hardware components while maintaining efficient FLR processing.
3Ease of operation
If multiple instances of classification tables are maintained for each function, then FLR isolation is simplified, but memory resources and device complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the classification table into multiple regions, with each region assigned to a specific function. This allows logical partitioning of a single physical memory block into function-specific segments. During FLR, only the affected function's region needs to be sanitized, providing isolation simplicity without requiring separate physical tables for each function, thus optimizing memory resource usage.
Data Source
AI summary
Methods and apparatus are provided for managing classification of packets within a multi-function input/output device, and for allowing the device's classification tables to be cleared in a non-blocking manner. The input/output device conveys multiple communication connections corresponding to multiple physical and/or virtual PCIe (Peripheral Component Interconnect Express) functions bound to software images executing on hosts. The device comprises gate logic configured to indicate statuses of the functions or the DMA engines bound to the functions. When the gate logic indicates a particular destination function is valid, the packet is transferred normally after being classified. A portion of the logic corresponding to a given function is reprogrammed to indicate the function is invalid when that function is reinitialized (e.g., FLR or Function Level Reset). The function's entries in packet classification tables are cleared afterward. When the logic indicates a function is invalid, packets destined for that function are dropped.