Packet Clock Recovery Using Sliding Window Accuracy Filtering

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Solution Overview

Problem

Current packet clock recovery methods using short message selection time windows often result in large clock recovery errors due to the uncertainty and randomness of Path Delay Value (PDV) in network environments, which are exacerbated by sudden changes in time delay.

Innovation Solution

A method combining a short message selection time window with a sliding time window to determine the accuracy of the first loop control value, using the sliding window to identify sudden changes and anomalous points, and generating a control parameter for the clock generator based on this accuracy to avoid large clock recovery errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a short message selection time window is used for packet clock recovery, then the ability to reflect clock changes rapidly is improved, but the risk of reflecting incorrect information due to sudden time delay changes increases

Engineering Contradiction:
Improveclock change reflection speedVSAvoidclock information accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent dynamically adjusts the message selection time window length based on network conditions. When time delay changes are detected, the window length is adapted to filter out incorrect clock information while maintaining the ability to reflect genuine clock changes rapidly. This dynamic adjustment resolves the contradiction by making the system responsive to changing conditions rather than using a fixed window length.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism that monitors the reliability of clock information obtained through the short message selection time window. When incorrect information is detected (indicating sudden time delay changes), the system adjusts its behavior to avoid using such information, thereby maintaining accuracy while preserving rapid response capability for genuine clock changes.

Inventive Principle:
Principle #23Feedback

2Productivity

If only a short message selection time window is used, then rapid clock tracking is achieved, but large clock recovery errors occur due to PDV uncertainty

Engineering Contradiction:
Improveclock tracking speedVSAvoidclock recovery accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent merges the short message selection time window method with additional verification mechanisms. By combining rapid clock tracking through short windows with reliability checks and adaptive filtering, the system achieves both fast clock tracking and high recovery accuracy, eliminating the trade-off between speed and precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the parameter of message selection time window length dynamically based on network conditions and detected time delay variations. This parameter adjustment allows the system to maintain rapid tracking when conditions are stable while filtering out errors when PDV uncertainty increases, thus achieving both high productivity and measurement precision.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2782272B1Method and apparatus for packet timing recovery
Publication Date: 2022.05.04 ZTE CORP
  • EP2782272B1 patent drawingFigure 1~2
  • EP2782272B1 patent drawingFigure 3~4
  • EP2782272B1 patent drawingFigure 5~6

AI summary

The present invention provides a method and an apparatus for packet clock recovery. The method includes: acquiring a first loop control value generated with a current short message selection time window; determining accuracy of the first loop control value by using a sliding time window, wherein the sliding time window is set up by using M forward consecutive short message selection time windows based on the current short message selection time window as a starting point; and generating a control parameter for a clock generator according to the determined accuracy to control clock generation and recover a packet clock. The problem in related art of larger clock recovery error resulted from the short message selection time window can be solved by adopting the present invention.