Embedded Packet Clock Signaling for Precise Network Time Sync
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Distributed computing environments face challenges in synchronizing time accurately and efficiently across multiple computing devices, as existing techniques like Network Time Protocol (NTP) are not sufficiently accurate or complex to implement, leading to difficulties in determining the priority of conflicting requests and maintaining a shared notion of time.
Innovation Solution
A method of transmitting clock signals within network packets using a clock distribution network, where the clock signal is embedded within network packets, allowing for additional metadata such as authentication and validation information, and utilizing a clock selection circuit like a Field Programmable Gate Array (FPGA) to ensure accurate synchronization across server computers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Network Time Protocol (NTP) is used to synchronize time between networked computers, then time synchronization is achieved, but the accuracy is insufficient and the system becomes too complex for wide-scale distributed computing platforms
Solution Approach 1:
The patent extracts the clock signal transmission from complex software protocols like NTP and implements it through dedicated hardware components (clock selection circuits, FPGAs) that operate independently of the software stack. This hardware-based approach provides more accurate time synchronization without the complexity of software-based time negotiation and adjustment protocols.
Solution Approach 2:
The patent introduces dedicated hardware intermediaries (clock selection circuits, FPGAs) that act as specialized components between the network interface and the system clock. These intermediaries handle time synchronization independently, providing accurate clock signals without requiring complex software protocols to negotiate and adjust time across the distributed system.
2Measurement precision
If dedicated hardware components are used for clock signal transmission, then time synchronization accuracy is improved, but hardware complexity increases
Solution Approach 1:
The patent designs the clock selection circuit and FPGA components to perform multiple functions: they not only transmit clock signals but also select between different time sources, validate incoming packets, and integrate with existing network infrastructure. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing hardware complexity while maintaining accuracy.
Solution Approach 2:
The hardware components are designed to autonomously perform clock signal selection, validation, and transmission without requiring external control or complex configuration. The clock selection circuit automatically selects the appropriate time source, and the FPGA self-configures to transmit clock signals embedded in network packets, reducing the operational complexity despite the added hardware.
3Loss of information
If clock signals are embedded within network packets, then additional metadata can be transmitted, but the network protocol complexity increases
Solution Approach 1:
The patent merges the clock signal transmission with existing network packet structures. Instead of creating a separate dedicated protocol, the clock signals are embedded within standard network packets, allowing simultaneous transmission of time information and metadata without requiring separate communication channels or complex protocol negotiations.
Solution Approach 2:
The network packets serve dual purposes: they carry both the embedded clock signals for time synchronization and metadata for additional information exchange. This multi-functionality allows the system to transmit multiple types of information through a single protocol structure, reducing the need for separate protocols and managing overall protocol complexity.
Data Source
AI summary
A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The network packets can include a preamble used to create phase alignment between a timing pulse and a bit position of a Start of Frame Delimiter (SFD) within the packet. The clock signal associated with the packet occurs when the SFD is detected. In one example, the SFD is detected when two consecutive bits of equal value are received and the timing of the clock signal is such that the clock signal occurs when the second consecutive bit is received. By including a clock signal within a packet, additional information can be transmitted with the clock signal. For example, authentication and validation information can be included, a time stamp, a message type, a frame check sequence, a clock status, etc.