Packet Combining Unit for DMA Transfer Efficiency
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Solution Overview
Problem
Existing packet processing systems face inefficiencies in handling high-frequency small packets, leading to increased processor load and reduced reception performance due to hardware interruptions and DMA transfer overhead, and require large hardware scales for restoring combined packets.
Innovation Solution
A packet processing apparatus that combines multiple small packets into a single combined packet and transfers it using DMA or collective writing, with a combined packet transferring unit that determines start addresses and writes packet lengths into a descriptor for efficient DMA transfer or writing, reducing hardware requirements and improving reception performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple small packets are processed individually with DMA transfer, then each packet can be transferred efficiently, but the processor load increases and reception performance decreases due to frequent hardware interruptions
Solution Approach 1:
The patent combines multiple small packets into a single combined packet before DMA transfer. The packet combining unit accumulates multiple received packets and merges them into one larger packet, which is then transferred to packet memory in a single DMA operation. This reduces the number of hardware interruptions and DMA transfers, thereby decreasing processor load while maintaining transfer efficiency.
2Productivity
If hardware scale is increased to restore combined packets into original packets, then packet restoration capability is improved, but hardware complexity and cost increase
Solution Approach 1:
The patent introduces a descriptor as an intermediary data structure that stores metadata about combined packets, including start addresses and packet lengths. This descriptor allows the system to track and restore original packets from the combined packet without requiring complex hardware restoration mechanisms. The descriptor acts as a software-based intermediary that simplifies the restoration process.
Solution Approach 2:
The patent replaces hardware-based packet restoration mechanisms with a software-based approach using descriptors. Instead of using complex hardware circuits to restore original packets from combined packets, the system uses software to read the descriptor information and perform restoration operations, thereby reducing hardware complexity and scale.
3Productivity
If buffer area size is increased to store combined packets, then packet combining capability is improved, but memory usage increases and waste is generated
Solution Approach 1:
The patent implements dynamic buffer management where the buffer area size is adjusted based on the actual packet combining requirements. The system allocates buffer space dynamically as packets are combined and releases it when packets are restored or transferred, ensuring that the buffer size matches the current operational needs rather than being statically oversized.
Solution Approach 2:
The patent changes the buffer management parameters from fixed allocation to dynamic allocation based on packet characteristics. The buffer area is allocated and released based on the actual size and number of packets being combined, allowing the system to optimize memory usage according to real-time traffic conditions and reduce waste.
Data Source
AI summary
A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.