Packet Control Apparatus Bus Throughput Optimization
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Solution Overview
Problem
In systems with multiple memory controllers and increased distances between sequence control points, the transmission of posted packets leads to delays, causing subsequent packets to be held back, which degrades throughput performance in packet communication systems, especially in PCI-based systems with peer-to-peer communication.
Innovation Solution
A packet control apparatus that separates the phase of packet transmission from the phase of processing permission notification, allowing subsequent packets to be transmitted before the completion of preceding posted packets, and using processing wait information to manage packet processing at the destination device, ensuring sequence control and improving internal bus efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequence control is performed near the memory controller to ensure posted packets are completed before subsequent packets are transmitted, then packet sequence integrity is maintained, but throughput performance degrades due to packet jams and delays
Solution Approach 1:
The patent segments the packet transmission process into two independent phases: (1) packet transmission phase where packets are sent to the destination device, and (2) processing permission notification phase where completion status is communicated back. This segmentation allows subsequent packets to be transmitted without waiting for preceding posted packet completion, maintaining sequence integrity while improving throughput.
Solution Approach 2:
The patent implements preliminary action by having the transmission source device send processing permission notifications to the transmission target device before actual packet processing occurs. This allows the target device to prepare for packet processing in advance, eliminating waiting delays and improving overall system throughput while maintaining proper sequencing.
2Reliability
If the transmission target device waits for completion of preceding posted packets before processing subsequent packets, then sequence control is maintained, but internal bus efficiency decreases due to idle waiting time
Solution Approach 1:
The patent implements a feedback mechanism where the transmission source device monitors the completion status of posted packets and sends processing permission notifications to the transmission target device. This feedback loop ensures sequence control is maintained while eliminating unnecessary waiting time, as the target device only processes packets when actually permitted to do so.
Solution Approach 2:
The transmission source device performs preliminary actions by sending processing permission notifications in advance before the target device needs to process packets. This allows the target device to be ready for processing without idle waiting, improving internal bus efficiency while maintaining sequence integrity.
3Productivity
If buffers are increased to prevent packet jams and allow continuous transmission, then throughput performance improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent segments the packet handling process into transmission and processing phases, allowing packets to be sent continuously without requiring large buffers to hold packets during processing. The processing permission notification mechanism ensures proper sequencing without needing extensive buffering capacity, reducing device complexity while maintaining high throughput.
Data Source
AI summary
A packet control apparatus includes a transmission source device configured to add processing wait information that indicates whether to permit immediate processing to a packet to be transmitted to a destination, and a transmission target device configured to, in a case where the processing wait information is added to the packet, wait for and receive a processing permission notification that indicates a completion of a preceding packet from the transmission source device, and process the packet, the transmission target device being a device of the destination, wherein the transmission source device and the transmission target device are coupled to each other through a bus.