High-Speed Data Packet Counting via Segmented Low-Bit Counter and RAM
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Solution Overview
Problem
Existing methods for counting data packets in network systems either occupy excessive logical resources or have slow operation speeds, particularly when dealing with multiple channels and high-speed data processing requirements.
Innovation Solution
A method and system that combines low bit counters and RAM to count packet pulse signals, sending a carry signal when full, and updating RAM addresses to achieve rapid calculation speeds while reducing logical resource usage, allowing for flexible counter resets without affecting other channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If registers are used to count data packets, then counting speed is rapid, but logical resource occupancy is excessive
Solution Approach 1:
The patent segments the counter into two parts: a low-bit counter (implemented with registers for fast counting) and a high-bit counter (implemented with RAM for storage). The low-bit counter handles frequent counting operations rapidly, while the high-bit counter in RAM stores the accumulated count values, thus dividing the counting function between speed-critical and storage-critical components.
Solution Approach 2:
The patent introduces a carry signal as an intermediary mechanism between the low-bit counter and the high-bit counter. When the low-bit counter overflows, it generates a carry signal that triggers an increment in the high-bit counter, enabling coordinated operation between the register-based fast counter and RAM-based storage counter without requiring full-register allocation for all count bits.
2Quantity of substance
If RAM is used to count data packets, then logical resource occupancy is reduced, but operation speed becomes slow
Solution Approach 1:
The counting system is segmented into a fast low-bit counter using registers and a storage-oriented high-bit counter using RAM. The low-bit counter handles the time-critical counting operations at high speed, while the RAM-based high-bit counter handles storage, thus assigning each component its optimal function based on its characteristics.
Solution Approach 2:
The low-bit counter continuously counts packet arrivals in advance, maintaining a running total in the fast register. Only when overflow occurs does the system need to interact with the slower RAM, thus performing the bulk of counting work preliminarily in the fast path before needing persistent storage.
3Device complexity
If all counters are reset together, then system simplicity is maintained, but flexibility is reduced
Solution Approach 1:
The counter reset functionality is segmented into channel-specific reset capabilities. Each channel's counter can be independently reset by setting its corresponding enable bit to 0, allowing selective resetting of individual channels without affecting others, thus providing flexibility while maintaining manageable complexity through modular control.
Data Source
AI summary
The disclosure provides a method for counting data packets, which includes the following steps: counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full; and acquiring data from an address of a Random Access Memory (RAM) corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address. The disclosure also provides a system for counting data packets. According to the technical scheme of the disclosure, the occupancy rate of logical resources is reduced while the counting of the data packets in a network is finished at a high speed.