Packet Protection CRC Circuit for Variable-Length Memory Data
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-throughput systems, existing memory systems require multiple CRC calculation circuits to handle variable-length data, leading to increased circuit area due to the need for circuits to calculate CRCs for data sizes such as 1-byte, 5-byte, 9-byte, and 13-byte data in addition to 4-byte and 8-byte data, which complicates error detection during data transfer.
Innovation Solution
A memory system with a packet protection circuit that includes a plurality of first CRC calculation circuits for M-byte data and a second CRC calculation circuit for L-byte data, where L is less than N, allowing the generation of a combined CRC to detect errors in variable-length data packets by dividing data into portions of multiple of 4 bytes and a remaining byte, reducing the need for multiple CRC circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CRC calculation circuits are provided for different data sizes (1-byte, 5-byte, 9-byte, 13-byte data in addition to 4-byte and 8-byte data), then error detection capability is maintained for all variable-length data, but the circuit area increases significantly
Solution Approach 1:
The patent applies universality by making the CRC calculation circuit adaptable to multiple data sizes through dynamic configuration. The circuit can be selectively enabled or disabled for different data size scenarios (1-byte, 4-byte, 5-byte, 8-byte, 9-byte, 13-byte data) without requiring separate dedicated circuits for each size. This multi-functional approach allows a single circuit structure to handle various packet formats and data lengths, maintaining error detection capability across all cases while avoiding the area overhead of multiple parallel circuits.
2Productivity
If CRC calculation is performed once per data input cycle for high throughput, then productivity is improved, but the device complexity increases due to the need for multiple specialized circuits
Solution Approach 1:
The patent applies dynamics by implementing a configurable CRC calculation circuit that can dynamically adjust its operation based on the actual data size and packet format. Rather than using fixed static circuits for each data size, the circuit can be programmed or configured at runtime to handle the specific data length being processed. This dynamic adaptability enables the system to maintain high throughput by processing data in single cycles while avoiding the complexity of permanently instantiated multiple specialized circuits.
Data Source
AI summary
A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.