Packet Data Communication for Power Semiconductor Switching Control
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Solution Overview
Problem
High voltage and high current power semiconductor switching devices are prone to failure due to noisy electrical environments, leading to cascading failures in systems where multiple devices are connected in series or parallel, and existing control methods lack efficient fault detection and synchronization techniques.
Innovation Solution
Implementing packet data communication techniques with a central controller and sub-controllers via shared and dedicated buses, using real-time and non-real-time data packets for synchronized switching control, fault detection, and error correction, allowing for rapid identification and management of faults across multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packet data communication techniques are implemented for controlling switching devices, then communication reliability is improved through error detection and correction, but system complexity increases due to additional processing overhead
Solution Approach 1:
The patent introduces packet data communication as an intermediary layer between the central controller and switching devices. This intermediary implements error detection and correction codes, allowing reliable communication without requiring complex direct control links. The packet structure acts as a mediator that handles error management, simplifying the overall system architecture while maintaining high reliability.
Solution Approach 2:
The patent employs redundant data transmission through packet copying and acknowledgment mechanisms. Control commands are transmitted as packets with error detection codes, and acknowledgments are copied back to verify successful reception. This copying approach ensures reliability without requiring complex error handling logic in the switching devices themselves.
2Manufacturing precision
If packet data communication is used for synchronized control, then control precision is improved through low latency, but processing time increases due to packet formatting and error correction
Solution Approach 1:
The patent implements preliminary formatting of control data into standardized packets with pre-calculated error detection and correction codes. By preparing the packet structure in advance rather than formatting during transmission, the system achieves low latency while maintaining high control precision. The switching devices receive pre-processed packets that require minimal additional processing.
Solution Approach 2:
The patent optimizes packet parameters such as data length, error correction code density, and transmission timing to balance processing time and control precision. By adjusting these parameters based on system requirements, the patent achieves low-latency communication suitable for synchronized control of power semiconductor devices while maintaining adequate error protection.
3Power
If multiple switching devices are controlled in series or parallel, then system power capacity is improved, but fault propagation risk increases leading to cascading failures
Solution Approach 1:
The patent segments the control system into independent switching devices, each with its own controller receiving individualized control packets. This segmentation isolates faults to individual devices or small groups, preventing cascading failures across the entire system. Each device can be controlled and monitored independently, allowing the system to maintain high power capacity through parallel/series configuration while limiting fault propagation.
Solution Approach 2:
The patent implements feedback mechanisms where each switching device sends status information back to the central controller via packet communication. The controller monitors individual device states and can detect faults early, taking corrective action before failures propagate. This feedback loop enables the system to maintain high power capacity while actively managing fault propagation risk through real-time monitoring and control.
Data Source
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AI summary
We describe techniques suitable for communicating switching data in a control system controlling, for example, kilovolts at hundreds of amps. The system comprises a central controller (110) coupled to sub - controllers (120) and thence to a plurality of switching device controllers (SDs,130), preferably in a tree - structure, each SD controlling a power semiconductor switching device such as an IGBT. The method includes formatting switching control data as one or more switching control data packets comprising data for controlling switching of a combination of the devices, sending these from the central controller to the switching device controllers, at the SDs formatting state data representing states of the switching devices controlled in combination into a plurality of acknowledgement data packets, and sending these back to the central controller. The techniques may be employed for controlling the synchronised switching of, potentially, tens, hundreds or thousands of power semiconductor switching devices.