Network Adapter Packet Descriptor Queue Management
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Solution Overview
Problem
Conventional network adapter architectures face performance limitations due to slow access times for external memory resources and data coherency issues when managing packet descriptors, leading to inefficiencies in queue management and increased latency.
Innovation Solution
Implementing a network adapter architecture with queue management logic that uses on-chip memory to store packet descriptors and minimizes external memory access by maintaining a queue register with indices to descriptors, allowing for efficient assignment and reuse of packet descriptors, thereby maximizing the use of on-chip resources and streamlining data coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If packet descriptors are stored in external memory resources, then storage capacity is increased, but access time increases and performance decreases
Solution Approach 1:
The patent segments the descriptor storage system into on-chip memory for frequently accessed descriptors and external memory for less frequently accessed descriptors. The queue management logic maintains a pool of descriptor indices in on-chip memory, while the actual descriptor data can be stored in external memory. This segmentation allows fast access to descriptor metadata while maintaining adequate storage capacity in external memory.
Solution Approach 2:
The patent introduces an intermediary mechanism - the queue management logic with descriptor pools and index registers - that mediates between on-chip memory and external memory. Instead of directly accessing external memory for every descriptor, the system uses on-chip descriptor pools as an intermediary cache layer, storing indices and metadata that enable fast access without frequent external memory transactions.
2Device complexity
If conventional linked list management is used, then implementation simplicity is maintained, but data coherency issues and latency increase
Solution Approach 1:
The patent extracts the coherency management function from the conventional linked list implementation and places it in dedicated queue management logic. Instead of relying on software to manage descriptor linked lists and handle coherency, the patent implements hardware-based queue management logic that automatically maintains descriptor pools, manages indices, and ensures data coherency through dedicated control circuits and status registers.
Solution Approach 2:
The queue management logic implements self-service mechanisms where the hardware automatically manages descriptor allocation, linkage, and coherency without requiring external software intervention. The descriptor pools self-manage their own indices and linkages through hardware pointers and status registers, eliminating the need for software to manually update linked lists and resolve coherency issues.
3Speed
If on-chip memory is used for packet descriptors, then access speed is improved, but available memory resources are limited
Solution Approach 1:
The patent implements dynamic descriptor pooling where the queue management logic can allocate and deallocate descriptor indices in on-chip memory based on current traffic demands. The descriptor pools are dynamically sized and managed, allowing the system to optimize the balance between on-chip storage and access speed based on real-time queue depths and traffic patterns, rather than using a fixed memory allocation.
4Productivity
If external memory access is minimized, then performance is improved, but storage capacity is reduced
Solution Approach 1:
The patent implements preliminary action by pre-allocating pools of descriptor indices in on-chip memory and pre-establishing the descriptor pool structures before actual packet processing begins. The queue management logic pre-loads descriptor indices and maintains ready-to-use pools, so that when packets arrive, the system can immediately allocate descriptors from pre-prepared pools without needing to access external memory for each individual descriptor allocation.
Data Source
AI summary
A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. Packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory.