Packet Engine PPI Credit Management
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Solution Overview
Problem
In network flow processors, managing and storing packet data from multiple sources into a single memory efficiently while allowing for effective processing and output is challenging, particularly due to resource constraints and the need for efficient allocation and deallocation of memory resources.
Innovation Solution
A packet engine is introduced that uses Packet Portion Identifier (PPI) Addressing Mode (PAM) for communication across a Command/Push/Pull (CPP) bus to manage memory allocation and deallocation, employing a PPI Allocation Table to allocate and de-allocate PPIs, and a Memory Allocation Table to manage memory space, enabling efficient storage and retrieval of packet portions using Linear Address Mode (LAM) for writing and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple PDRSDs manage and handle storing packet portions into memory independently, then each PDRSD can control its own memory operations, but memory management complexity increases and resource contention occurs
Solution Approach 1:
A packet engine is introduced as an intermediary component between PDRSDs and memory. The packet engine receives packet portions from multiple PDRSDs, manages their storage in memory using PPI addressing, and coordinates access to avoid contention. This mediator simplifies the overall system by centralizing memory management functions while allowing each PDRSD to operate independently for packet reception.
2Adaptability or versatility
If packet portions are stored in memory without structured allocation, then memory usage is flexible, but allocation and deallocation of memory resources becomes inefficient
Solution Approach 1:
The memory management system is segmented into distinct structures: a PPI Allocation Table for tracking allocated packet portion identifiers, a Memory Allocation Table for managing physical memory blocks, and credit-based accounting mechanisms. This segmentation allows efficient allocation and deallocation operations while maintaining flexibility in how packet portions are stored and accessed.
Solution Approach 2:
The system implements credit-based feedback mechanisms where PDRSDs receive credits when packet portions are successfully stored in memory. The packet engine tracks available credits and allocates memory resources accordingly, providing feedback loops that optimize memory utilization efficiency while maintaining adaptability.
3Productivity
If multiple specialized processors access memory simultaneously, then processing throughput increases, but memory contention reduces system performance
Solution Approach 1:
The packet engine performs preliminary actions by pre-managing memory allocation before packet processing occurs. It allocates memory blocks and assigns PPIs in advance, establishing memory access pathways before multiple processors need to access the memory. This preliminary organization reduces contention and improves reliability during simultaneous processing operations.
Data Source
AI summary
In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.