Network Packet Error Correction for Low-Power Storage Microservers
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Solution Overview
Problem
Current data storage solutions, such as public cloud storage and traditional x86-based private clouds, face high costs, performance bottlenecks, and privacy concerns, while alternative solutions like SSDs and cold storage are expensive or unsuitable for real-time big data analytics.
Innovation Solution
The implementation of a storage microserver architecture using ARM processors and coprocessors integrated onto a system on a chip (SoC), optimized software, and error correction codes like erasure coding to provide cost-effective, high-performance, and reliable data storage with reduced hardware costs and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If public cloud storage or traditional x86-based private clouds are used, then data storage and access functionality is provided, but hardware costs and power consumption are high
Solution Approach 1:
The patent changes the fundamental parameter of processor architecture from x86 to ARM, which provides comparable computational reliability while significantly reducing power consumption and hardware costs. This parameter change enables the system to maintain data storage reliability through software optimization and error correction mechanisms while operating in a lower power regime suitable for edge devices and cost-effective deployments
2Productivity
If SSDs are used for data storage, then I/O performance is improved, but hardware costs increase
Solution Approach 1:
The patent segments the storage system into multiple components: ARM processor for control, coprocessors for specialized operations, and traditional hard disk drives for bulk storage. This segmentation allows the system to achieve high I/O performance through optimized software and parallel processing while using cost-effective mechanical storage devices instead of expensive SSDs for all storage needs
Solution Approach 2:
The patent replaces the need for mechanically complex SSD controllers and management systems with a simplified ARM-based controller that uses software optimization and error correction codes to achieve comparable or superior performance, thereby reducing hardware costs while maintaining I/O productivity
3Quantity of substance
If cold storage approaches are used, then hardware costs are reduced, but suitability for real-time big data analytics deteriorates
Solution Approach 1:
The patent introduces dynamic elements including coprocessors that can be activated based on workload requirements, and software that dynamically manages data between storage devices and processing units. This dynamic architecture enables the system to transition between low-power storage mode and high-performance analytics mode, making cold storage approaches suitable for real-time big data analytics when needed
Solution Approach 2:
The patent creates a universal storage system that can perform multiple functions: cost-effective bulk storage, real-time analytics processing, and error correction. The ARM processor with coprocessors and error correction codes enables the system to handle both archival storage and active analytics workloads, making hardware cost reduction compatible with real-time analytics capability
4Reliability
If error correction codes like erasure coding are implemented, then data recovery reliability is improved, but processing complexity increases
Solution Approach 1:
The patent extracts the complex error correction processing from the main ARM processor and implements it in dedicated coprocessors or hardware acceleration units. This extraction reduces the processing complexity burden on the main processor while maintaining enhanced data recovery reliability through specialized error correction code implementation
Data Source
AI summary
In one embodiment, a method is provided. The method includes receiving a request for a first set of data stored on a data storage system from a computing device. The method also includes retrieving the first set of data from a data storage device of the data storage system. The method further includes generating a set of codewords based on the first set of data and an error correction code. The method further includes transmitting a set of network packets to the computing device. Each network packet of the set of network packets comprises a codeword from the set of codewords.