Network Packet FEC Offload Using a Dedicated Hardware Engine

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Solution Overview

Problem

Current packet transmission processes face challenges in meeting high throughput requirements due to the computational intensity of forward error correction (FEC) encoding and decoding, which are typically handled by CPUs with limited capabilities.

Innovation Solution

Implementing FEC encoding and decoding tasks in a target hardware engine within network devices, rather than the CPU, to reduce CPU overhead and enhance processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FEC encoding and decoding are performed by CPU, then packet loss recovery is achieved, but computing capability and computing rate are limited, making it difficult to meet large throughput requirements

Engineering Contradiction:
Improvepacket loss recoveryVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a hardware engine as an intermediary component between the CPU and the FEC encoding/decoding process. This hardware engine specifically handles the computationally intensive FEC operations, allowing the CPU to focus on other tasks while maintaining high throughput and reliability simultaneously

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If FEC encoding and decoding are performed by CPU, then packet recovery function is implemented, but CPU overhead is high and computing rate is limited

Engineering Contradiction:
Improveoriginal packet recoveryVSAvoidcomputing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the software-based FEC encoding/decoding implementation in the CPU with a dedicated hardware engine. This substitution of computational mechanism dramatically reduces computing time and CPU overhead while maintaining the packet recovery function

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11695502B2Packet processing method and apparatus, and chip
Publication Date: 2023.07.04 HUAWEI TECH CO LTD
  • US11695502B2 patent drawing
  • US11695502B2 patent drawing
  • US11695502B2 patent drawing

AI summary

A packet processing method includes generating, by a processor of a network device, a first encoding task based on M original packets in a to-be-processed first data stream, where M is a positive integer, and where the first encoding task instructs to encode the M original packets; and performing, by a target hardware engine of the network device and based on the first encoding task, forward error correction (FEC) encoding on the M original packets to obtain R redundant packets, where R is a positive integer.