Packet Flow Distribution Across Multi-Core Processors for Load Balancing
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Solution Overview
Problem
Existing multi-core processor systems face inefficiencies in packet flow distribution, leading to unequal load balancing and reduced per-flow throughput due to traditional static hash-based distribution strategies, which result in overutilization of some cores and underutilization of others, limiting overall system performance.
Innovation Solution
A method and electronic device that utilize a combination of try-lock and ticket-lock mechanisms, along with core parameters, to dynamically distribute packet flows among processor cores, ensuring equitable load balancing and maximizing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional static hash-based distribution strategy is used, then implementation simplicity is maintained, but load balancing becomes unequal and per-flow throughput is reduced
Solution Approach 1:
The patent transitions from static hash-based distribution to dynamic packet flow distribution. The system continuously monitors core parameters (utilization, queue depth, processing capacity) and adaptively assigns packets to cores based on real-time conditions, enabling the distribution strategy to evolve with system state changes and achieve optimal load balancing.
Solution Approach 2:
The patent changes the distribution criterion from fixed hash values to dynamic core parameters including utilization metrics, queue depths, and processing capacities. By continuously evaluating these parameters and selecting cores based on current system state, the patent achieves both simplicity and high per-flow throughput simultaneously.
2Device complexity
If numerous data flows are coupled to a single worker core, then data decomposition is simplified, but load balancing deteriorates and some cores become overutilized while others remain underutilized
Solution Approach 1:
The patent segments the packet flow distribution decision-making process into multiple components: core parameter monitoring, dynamic evaluation, and adaptive assignment. Rather than简单地 decomposing data flows, the system segments the distribution logic to evaluate multiple cores and select the most appropriate one based on real-time parameters, preventing overutilization of single cores.
Solution Approach 2:
The patent implements dynamic load balancing by continuously monitoring core utilization, queue depths, and processing capacities. The system adapts its distribution strategy in real-time, assigning packets to cores based on current load conditions rather than fixed decomposition rules, thereby achieving both simplicity and balanced resource utilization.
3Device complexity
If feedback mechanism throughput is processed on the same overloaded worker core, then system structure is simplified, but overall system performance is degraded
Solution Approach 1:
The patent segments feedback processing from the main data flow processing by identifying and separating feedback packets. The system monitors packet types and routes feedback mechanisms to appropriate cores, preventing feedback overhead from contributing to core overload and maintaining clear separation between data plane and control plane functions.
Solution Approach 2:
The patent introduces an intermediary mechanism that identifies feedback packets and redirects them to suitable cores. This intermediary layer prevents feedback processing from exacerbating load on already overloaded cores while maintaining simplified overall system structure through a unified distribution framework.
Data Source
AI summary
An example method for distributing packet flow by an electronic device including a plurality of processor cores may include receiving a plurality of packet flows for validation; validating the plurality of packet flows by a processor core(s) of the plurality of processor cores based on a validation parameter(s); sequentially distributing the plurality of validated packet flows among the plurality of processor cores for processing based on a combination of a try-lock and a ticket-lock or a core parameter; and transmitting the plurality of distributed packet flows to an electronic entity by the processor core of the plurality of processor cores.