Packet Fragment Mapping for Accurate Non-Leading Flow Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Network devices improperly process non-leading packet fragments due to the lack of transport layer (Layer 4) header fields, leading to issues in network address translation and other flow-based processing.

Innovation Solution

Implementing a flow cache and a fragment mapping table in network devices to identify and process non-leading packet fragments by mapping their Layer 3 header information to flow cache entries, ensuring proper handling of packet fragments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If network devices process non-leading packet fragments using traditional methods, then processing speed is maintained, but processing accuracy deteriorates due to lack of transport layer header fields

Engineering Contradiction:
Improveprocessing accuracyVSAvoidprocessing mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a fragment mapping table as an intermediary structure that maps Layer 3 header information to flow cache entries. This mediator enables non-leading fragments to access flow information indirectly through the mapping table, resolving the accuracy issue without requiring direct access to transport layer headers in the fragments themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary actions by pre-establishing the fragment mapping table and flow cache entries before processing non-leading fragments. The mapping table is populated in advance with Layer 3 header information, enabling accurate processing to occur without requiring complex real-time analysis during fragment processing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If network devices maintain flow cache and fragment mapping table, then processing accuracy of non-leading fragments improves, but device complexity increases

Engineering Contradiction:
Improvefragment processing reliabilityVSAvoiddata structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The flow cache and fragment mapping table serve multiple functions: they enable accurate processing of non-leading fragments, maintain flow state information, and provide a mechanism for network address translation. This multi-functionality justifies the added complexity by consolidating multiple processing requirements into unified structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the parameter approach by shifting from relying on transport layer header fields (which are absent in non-leading fragments) to using Layer 3 header information and flow cache entries. This parameter change enables reliable processing despite the structural limitations of non-leading fragments.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If network devices use Layer 3 header information to identify flow entries, then processing of non-leading fragments becomes accurate, but information completeness decreases

Engineering Contradiction:
Improveflow identification accuracyVSAvoidtransport layer header information
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The fragment mapping table creates a copy or reference to flow cache entries using Layer 3 header information. Instead of requiring the original transport layer header information to be present in non-leading fragments, the system copies the necessary flow identification data from the mapping table, enabling accurate processing while accepting the information loss in the fragment itself.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250392543A1Handling of Packet Fragments
Publication Date: 2025.12.25 ARISTA NETWORKS INC
  • US20250392543A1 patent drawing
  • US20250392543A1 patent drawing
  • US20250392543A1 patent drawing

AI summary

A network device may include packet processing circuitry and memory circuitry accessible by the packet processing circuitry to perform traffic processing operations. The packet processing circuitry may maintain, on the memory circuitry, a flow cache and a fragment mapping table. A leading fragment of an original un-fragmented packet may be used to provide an entry in the flow cache and to provide an entry in the fragment mapping table. The entry in the fragment mapping table and consequently the entry in the flow cache may be used to process one or more non-leading fragments of the original un-fragmented packet.