Multi-Channel Packet Fragment Scheduler for Memory Area Reduction

The patent segments the high-speed data stream into multiple lower-speed channels, allowing a single memory port to handle multiple channels sequentially. The data assembler divides incoming data into channel-specific segments that can be processed and stored in separate FIFO buffers, reducing the need for high-bandwidth memory interfaces and large memory sizes.

The patent implements dynamic channel assignment and memory allocation where the system adapts to varying channel activity patterns. The data assembler dynamically assigns incoming data to appropriate channel buffers based on current channel states, and the memory system dynamically adjusts its operation mode between single-port and multi-port based on the number of active channels, optimizing resource utilization.

The patent employs periodic channel activation and memory access patterns where channels are serviced in a systematic sequence rather than simultaneously. The data assembler periodically switches between channel buffers in a round-robin or priority-based manner, allowing the single memory port to maintain high utilization efficiency while preserving storage speed through optimized access timing.

The patent ensures continuous useful action by implementing overlap techniques where data preparation for one channel occurs during the memory access of another channel. The data assembler continuously processes incoming data and prepares it for storage, while the memory system continuously services active channels, minimizing idle time and maintaining high storage throughput without requiring multiple simultaneous write ports.