Asynchronous Packet Gate Control for Deterministic Transmission Order

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Solution Overview

Problem

Current communication networks face challenges in maintaining low latency and Packet Delay Variation (PDV) for time-critical traffic, particularly in the fronthaul domain of mobile communication networks, where existing methods like traffic classification and time-based gating are inadequate in ensuring deterministic packet transmission order among competing packet flows.

Innovation Solution

A system comprising network elements with selectively switchable packet gates and queues, where the switching is controlled asynchronously based on events associated with other queues to ensure a relative transmission order among packet flows, avoiding race conditions and PDV accumulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If time-based gating is used to reduce packet delay and PDV, then packet transmission order is improved, but time synchronization complexity increases

Engineering Contradiction:
Improvepacket transmission orderVSAvoidtime synchronization
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism (gate control list and gate vectors) that mediates between time-based gating requirements and actual packet transmission. The gate control list acts as a pre-computed schedule that translates complex time synchronization requirements into simple gate open/close operations at each network element, eliminating the need for continuous time synchronization while maintaining deterministic packet transmission order.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by pre-computing gate control lists and gate vectors before packet transmission. The gate control list is prepared in advance with specific time points and gate states, allowing network elements to execute deterministic packet forwarding without real-time synchronization. This pre-planning eliminates the complexity of time synchronization during actual packet transmission.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If additional buffering is used to reduce PDV, then packet delay variation is reduced, but packet latency increases

Engineering Contradiction:
Improvepacket delay variationVSAvoidpacket latency
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the gate control list adaptive rather than static. The gate control list can be dynamically adjusted based on network conditions, traffic patterns, and measured PDV. This allows the system to optimize the balance between buffering and transmission timing, reducing PDV without unnecessarily increasing latency. The dynamic nature enables the system to respond to changing conditions and minimize both PDV and latency simultaneously.

Inventive Principle:
Principle #15Dynamics

3Speed

If packet gates are constantly open to reduce latency, then packet transmission speed is improved, but PDV control capability is reduced

Engineering Contradiction:
Improvepacket transmission speedVSAvoidPDV control
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies periodic action by implementing regular gate opening/closing cycles based on the gate control list. Instead of keeping gates constantly open or closed, the system periodically switches gate states according to pre-computed time points. This periodic gating maintains high transmission speed during open periods while providing deterministic control over packet transmission order and PDV during the structured open/close cycles.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11323384B2Packet processing technique for a communication network
Publication Date: 2022.05.03 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11323384B2 patent drawing
  • US11323384B2 patent drawing
  • US11323384B2 patent drawing

AI summary

A system comprising one or more network elements and configured to process at least first and second packet flows. The system comprises a first packet gate selectively switchable between an open state for packet transmission and a closed state and an associated first packet queue. The first packet gate and the first packet queue are configured to handle first packet flow packets. The system further comprises a second packet queue configured to handle second packet flow packets. Moreover, the system comprises at least one processor configured to control switching of the first packet gate between the open state and the closed state based on the occurrence of a first event associated with the second packet queue to trigger transmission of the first packet flow packets in a relative transmission order among the first packet flow packets and the second packet flow packets.