Packet Switched Data Header and Payload Bit Processing

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Solution Overview

Problem

Existing packet-switched data transfer technologies face inefficiencies in processing header and payload bits, particularly in ensuring low transfer delay and error protection for real-time multimedia communications like VoIP, where strict quality of service requirements are not adequately met due to uniform error protection across varying bit classes.

Innovation Solution

Classifying header and payload bits into multiple classes based on their importance and processing them separately using specific mechanisms, such as error protection algorithms, to optimize error protection and reduce encoded frame size by applying varying degrees of encoding to each class.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform error protection is applied to all bits in the AMR frame, then error protection coverage is maximized, but encoding efficiency and quality of service are degraded due to over-protection of less sensitive bits

Engineering Contradiction:
Improveerror protectionVSAvoidencoding efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different error protection mechanisms to different bit classes within the AMR frame. Class A bits receive strong error protection (CRC protection), while Class B and C bits receive progressively weaker protection. This local differentiation optimizes encoding efficiency by applying protection only where needed, resolving the contradiction between comprehensive error protection and encoding efficiency.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If fixed rate speech codec is used for transport in PS domain, then compatibility is maintained, but quality of service requirements cannot be adequately met due to inability to differentiate bit protection

Engineering Contradiction:
ImproveQoS adaptabilityVSAvoidquality of service
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the AMR frame into three distinct bit classes (A, B, and C) based on their sensitivity to errors. Each class is then processed with different error protection mechanisms, enabling the system to adapt to varying QoS requirements while maintaining compatibility with fixed rate speech codecs. This segmentation allows differentiated protection without compromising codec compatibility.

Inventive Principle:
Principle #1Segmentation

3Reliability

If all bits are protected with maximum error protection, then reliability is maximized, but encoded frame size increases reducing transfer efficiency

Engineering Contradiction:
Improveerror protectionVSAvoidencoded frame size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements local quality differentiation by applying maximum error protection (CRC) only to Class A bits, while applying lighter protection to Class B and C bits. This selective protection approach maximizes reliability for the most critical bits while minimizing the overall encoded frame size, thereby improving transfer efficiency.

Inventive Principle:
Principle #3Local quality

4Productivity

If differentiated processing is applied to header and payload bits, then processing efficiency is improved, but system complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality differentiation by processing header bits and payload bits differently based on their characteristics. Header bits receive specific processing tailored to their control function, while payload bits receive processing adapted to their data function. This differentiation improves processing efficiency while managing complexity through structured, rule-based processing for each bit type.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7769045B2Method and apparatus for processing header bits and payload bits
Publication Date: 2010.08.03 GOOGLE TECHNOLOGY HOLDINGS LLC
  • US7769045B2 patent drawing
  • US7769045B2 patent drawing
  • US7769045B2 patent drawing

AI summary

A method (200) and an apparatus (500) in a packet switched data transfer system for processing header bits and payload bits in a frame of bits are disclosed. The header bits are classified into a first predetermined class of bits and into a second predetermined class of bits (204), the payload bits are classified into the first predetermined class of bits and into the second predetermined class of bits (206), the first predetermined class of bits are processed in accordance with a first predetermined mechanism (208), and the second predetermined class of bits are processed in accordance with a second predetermined mechanism (210).