Packet Processing Latency Control via FIFO Pointer Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing packet processing technologies in communication networks face challenges in maintaining equal latency for different packets passing through forwarding devices, which is critical for services like CPRI, SDH, and PDH, as latency variations can be unacceptable and currently unmanageable.
Innovation Solution
A method and apparatus that determine and control the latency of packets in a FIFO memory by calculating a target latency, which includes a processing time interval, a buffer-to-FIFO memory interval, and a FIFO-to-egress port interval, ensuring all packets experience an equal latency by adjusting the write and read pointers accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the forwarding device performs table lookup operations on different packets, then the packets can be processed and forwarded, but the time intervals needed for table lookup operations are unequal, causing latency variation
Solution Approach 1:
The patent pre-calculates and pre-determines the latency that each packet will experience in the FIFO memory before the packet actually passes through. By determining the latency in advance based on the processing time interval and fixed latencies, the system can compensate for the variable processing times of different packets, ensuring that all packets experience equal total latency despite different table lookup durations
Solution Approach 2:
The patent implements a feedback mechanism where the determined latency information is used to adjust the write and read pointers of the FIFO memory. The system continuously monitors the processing time interval and adjusts the pointer positions to compensate for variations, creating a closed-loop control system that maintains equal latency for all packets
2Adaptability or versatility
If the forwarding device processes different packets with different processing times, then various packet types can be handled flexibly, but the latencies of different packets become unequal
Solution Approach 1:
The patent changes the parameter of FIFO memory latency dynamically based on the processing time interval. By adjusting the latency parameter in the FIFO memory (through pointer adjustments) to compensate for variations in processing time, the system maintains equal total latency while allowing flexible processing of different packet types with different processing requirements
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Embodiments of the present invention provide a packet processing method and apparatus. After receiving a packet, a first network device processes the packet, and determines a first latency of the processed packet in a FIFO memory, where: the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the second latency includes a third latency, and the third latency includes a time interval for processing the packet. That is, the time interval for processing the packet is taken into consideration in determining of the first latency. In addition, the determining of the first latency enables a latency generated when the packet passes through the first network device to be equal to the target latency. Therefore, in the foregoing technical solutions, a latency generated when a packet passes through a network device may be enabled to be equal to a certain value.