Packet Matching Pipeline Prefetching Reducing Memory Access Latency
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Solution Overview
Problem
Current network devices face slow packet matching speeds due to frequent memory access during the forwarding of IP or NDN packets, which can lead to delayed packet forwarding when handling a large number of packets.
Innovation Solution
The method involves adding data packets into multiple pipelines, each configured as a decision tree with different prefix lengths, where hash values are calculated and output interface data is prefetched asynchronously from memory, allowing for caching and reducing the need for subsequent memory access, enabling faster packet matching and forwarding by allowing new packets to be processed as soon as previous ones are forwarded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CPU accesses memory multiple times to complete packet matching using FIB and decision tree, then packet matching accuracy is ensured, but packet matching speed becomes slow
Solution Approach 1:
The patent pre-calculates hash values for all possible prefix lengths and stores them in a hash table before packet arrival. When a packet arrives, the system directly retrieves pre-computed hash values and corresponding output interfaces from the hash table, eliminating the need for multiple sequential memory accesses during actual packet matching. This preliminary preparation of data structures resolves the contradiction by trading off initial setup time for significantly faster real-time packet matching.
2Productivity
If the system processes packets sequentially with multiple memory accesses, then matching accuracy is maintained, but forwarding timeliness deteriorates
Solution Approach 1:
The system pre-computes and stores hash values for all prefix lengths in advance, so that during packet forwarding, the CPU can directly retrieve matching results from the pre-built hash table without performing multiple memory accesses. This preliminary preparation enables high-speed packet forwarding while maintaining matching accuracy.
Solution Approach 2:
The patent creates a hash table that copies and organizes FIB table entries with pre-computed hash values for different prefix lengths. This copied and reorganized data structure allows the system to quickly retrieve matching information without accessing the original FIB table multiple times, thereby improving forwarding throughput and reducing delay.
3Productivity
If the CPU performs synchronous memory access for each packet matching operation, then data accuracy is ensured, but processing efficiency decreases
Solution Approach 1:
The system performs preliminary computation of hash values and stores them in a hash table with their corresponding output interfaces. During packet matching, the system retrieves these pre-computed values, ensuring both accuracy (by using pre-calculated correct values) and efficiency (by avoiding repeated memory accesses and synchronous waiting).
Data Source
AI summary
A method and apparatus for packet matching, a network device, and a medium are disclosed, which includes adding N first data packets into N pipelines and configuring a stage for each pipeline as a root node of a decision tree; calculating a first hash value for a first pipeline in the N pipelines, and asynchronously prefetching a first output interface data corresponding to the first hash value from a memory, calculating a second hash value for a second pipeline in the N pipelines while prefetching the first output interface data from the memory, obtaining the first output interface data from the cache when calculation of the hash value for each pipeline is finished, deleting the first data packet when the first output interface data is characterized as being used to forward the first data packet in the first pipeline and adding a second data packet into the first pipeline.